Lines Matching refs:SRA
980 if (Opc == ISD::SRA)
1221 case ISD::SRA: return visitSRA(N);
1307 case ISD::SRA:
2026 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2039 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
2045 return SRA;
2047 AddToWorkList(SRA.getNode());
2048 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2225 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2227 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2477 // For each of OP in SHL/SRL/SRA/AND...
2482 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2827 // fold (and (sra)) -> (and (srl)) when possible.
3851 HighBitSet = false; // We can only transform sra if the high bit is clear.
3854 HighBitSet = true; // We can only transform sra if the high bit is set.
3859 HighBitSet = false; // We can only transform sra if the high bit is clear.
3874 BinOpLHSVal->getOpcode() != ISD::SRA &&
3885 if (N->getOpcode() == ISD::SRA) {
4094 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4095 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4129 // fold (sra c1, c2) -> (sra c1, c2)
4131 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
4132 // fold (sra 0, x) -> 0
4135 // fold (sra -1, x) -> -1
4138 // fold (sra x, (setge c, size(x))) -> undef
4141 // fold (sra x, 0) -> x
4144 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4158 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4159 if (N1C && N0.getOpcode() == ISD::SRA) {
4164 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4169 // fold (sra (shl X, m), (sub result_size, n))
4209 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4214 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4217 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4221 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4234 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
4236 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
4356 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4357 // bit, which is unmodified by sra.
4359 if (N0.getOpcode() == ISD::SRA)
4672 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4690 ISD::SRA, DL, VT, LHS,
5875 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5876 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5881 // We can turn this into an SRA iff the input to the SRL is already sign
5885 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
11204 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
11211 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
11230 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
11270 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
11368 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
11382 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
