Lines Matching refs:Op0
402 unsigned Op0 = getRegForValue(I->getOperand(0));
403 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
439 ISDOpcode, Op0, Op0IsKill, CF);
457 Op0, Op0IsKill,
893 unsigned Op0 = getRegForValue(I->getOperand(0));
894 if (Op0 == 0)
909 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
915 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1066 const Value *Op0 = EVI->getOperand(0);
1067 Type *AggTy = Op0->getType();
1071 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1074 else if (isa<Instruction>(Op0))
1075 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1238 unsigned /*Op0*/, bool /*Op0IsKill*/) {
1244 unsigned /*Op0*/, bool /*Op0IsKill*/,
1260 unsigned /*Op0*/, bool /*Op0IsKill*/,
1267 unsigned /*Op0*/, bool /*Op0IsKill*/,
1274 unsigned /*Op0*/, bool /*Op0IsKill*/,
1285 unsigned Op0, bool Op0IsKill,
1304 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1318 Op0, Op0IsKill,
1354 unsigned Op0, bool Op0IsKill) {
1358 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1362 .addReg(Op0, Op0IsKill * RegState::Kill);
1365 .addReg(Op0, Op0IsKill * RegState::Kill);
1375 Op0, bool Op0IsKill,
1380 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1385 .addReg(Op0, Op0IsKill * RegState::Kill)
1389 .addReg(Op0, Op0IsKill * RegState::Kill)
1399 unsigned Op0, bool Op0IsKill,
1405 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1411 .addReg(Op0, Op0IsKill * RegState::Kill)
1416 .addReg(Op0, Op0IsKill * RegState::Kill)
1427 unsigned Op0, bool Op0IsKill,
1433 MRI.constrainRegClass(Op0, RC);
1437 .addReg(Op0, Op0IsKill * RegState::Kill)
1441 .addReg(Op0, Op0IsKill * RegState::Kill)
1451 unsigned Op0, bool Op0IsKill,
1456 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1460 .addReg(Op0, Op0IsKill * RegState::Kill)
1465 .addReg(Op0, Op0IsKill * RegState::Kill)
1476 unsigned Op0, bool Op0IsKill,
1481 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1485 .addReg(Op0, Op0IsKill * RegState::Kill)
1489 .addReg(Op0, Op0IsKill * RegState::Kill)
1499 unsigned Op0, bool Op0IsKill,
1505 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1510 .addReg(Op0, Op0IsKill * RegState::Kill)
1515 .addReg(Op0, Op0IsKill * RegState::Kill)
1526 unsigned Op0, bool Op0IsKill,
1532 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1537 .addReg(Op0, Op0IsKill * RegState::Kill)
1542 .addReg(Op0, Op0IsKill * RegState::Kill)
1585 unsigned Op0, bool Op0IsKill,
1588 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1590 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1591 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1594 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1600 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1601 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
