Lines Matching refs:RegState
1362 .addReg(Op0, Op0IsKill * RegState::Kill);
1365 .addReg(Op0, Op0IsKill * RegState::Kill);
1385 .addReg(Op0, Op0IsKill * RegState::Kill)
1386 .addReg(Op1, Op1IsKill * RegState::Kill);
1389 .addReg(Op0, Op0IsKill * RegState::Kill)
1390 .addReg(Op1, Op1IsKill * RegState::Kill);
1411 .addReg(Op0, Op0IsKill * RegState::Kill)
1412 .addReg(Op1, Op1IsKill * RegState::Kill)
1413 .addReg(Op2, Op2IsKill * RegState::Kill);
1416 .addReg(Op0, Op0IsKill * RegState::Kill)
1417 .addReg(Op1, Op1IsKill * RegState::Kill)
1418 .addReg(Op2, Op2IsKill * RegState::Kill);
1437 .addReg(Op0, Op0IsKill * RegState::Kill)
1441 .addReg(Op0, Op0IsKill * RegState::Kill)
1460 .addReg(Op0, Op0IsKill * RegState::Kill)
1465 .addReg(Op0, Op0IsKill * RegState::Kill)
1485 .addReg(Op0, Op0IsKill * RegState::Kill)
1489 .addReg(Op0, Op0IsKill * RegState::Kill)
1510 .addReg(Op0, Op0IsKill * RegState::Kill)
1511 .addReg(Op1, Op1IsKill * RegState::Kill)
1515 .addReg(Op0, Op0IsKill * RegState::Kill)
1516 .addReg(Op1, Op1IsKill * RegState::Kill)
1537 .addReg(Op0, Op0IsKill * RegState::Kill)
1538 .addReg(Op1, Op1IsKill * RegState::Kill)
1542 .addReg(Op0, Op0IsKill * RegState::Kill)
1543 .addReg(Op1, Op1IsKill * RegState::Kill)
