Lines Matching refs:EXTLOAD
276 // Only do this if the target has a native EXTLOAD instruction from
278 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
291 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
378 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
493 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
589 // with a "move to register" or "extload into register" instruction, then
947 // that these bits are zero. It is also useful for EXTLOAD, since it
954 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
987 assert(!SrcVT.isVector() && "Unsupported extload!");
1000 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1030 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1097 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1103 case ISD::EXTLOAD:
1123 assert(ExtType != ISD::EXTLOAD &&
1124 "EXTLOAD should always be supported!");
1125 // Turn the unsupported load into an EXTLOAD followed by an
1127 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1448 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1799 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2580 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
3139 // EXTLOAD pair, targeting a temporary location (a stack slot).
