Lines Matching refs:ISD
278 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
291 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
308 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
325 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
366 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
368 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
378 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
390 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
414 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
423 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
432 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
446 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
448 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
449 ISD::ANY_EXTEND, dl, VT, Result);
485 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
486 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
493 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
507 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
530 ISD::LoadExtType HiExtType = LD->getExtensionType();
533 if (HiExtType == ISD::NON_EXTLOAD)
534 HiExtType = ISD::ZEXTLOAD;
539 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
553 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
555 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
565 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
566 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
568 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
606 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
610 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
611 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
631 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
694 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
701 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
728 switch (TLI.getOperationAction(ISD::STORE, VT)) {
750 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
753 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
806 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
819 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
828 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
837 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
868 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
886 ISD::LoadExtType ExtType = LD->getExtensionType();
887 if (ExtType == ISD::NON_EXTLOAD) {
922 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
962 ISD::LoadExtType NewExtType =
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
972 if (ExtType == ISD::SEXTLOAD)
974 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
977 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
979 Result = DAG.getNode(ISD::AssertZext, dl,
1002 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1009 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1018 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1022 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1027 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1038 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1040 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1048 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1052 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1057 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1097 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1103 case ISD::EXTLOAD:
1105 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1107 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1108 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1123 assert(ExtType != ISD::EXTLOAD &&
1127 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1132 if (ExtType == ISD::SEXTLOAD)
1133 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1158 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1170 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1177 case ISD::INTRINSIC_W_CHAIN:
1178 case ISD::INTRINSIC_WO_CHAIN:
1179 case ISD::INTRINSIC_VOID:
1180 case ISD::STACKSAVE:
1183 case ISD::VAARG:
1189 case ISD::SINT_TO_FP:
1190 case ISD::UINT_TO_FP:
1191 case ISD::EXTRACT_VECTOR_ELT:
1195 case ISD::FP_ROUND_INREG:
1196 case ISD::SIGN_EXTEND_INREG: {
1201 case ISD::ATOMIC_STORE: {
1206 case ISD::SELECT_CC:
1207 case ISD::SETCC:
1208 case ISD::BR_CC: {
1209 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1210 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1211 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1213 ISD::CondCode CCCode =
1217 if (Node->getOpcode() == ISD::SELECT_CC)
1225 case ISD::LOAD:
1226 case ISD::STORE:
1231 case ISD::CALLSEQ_START:
1232 case ISD::CALLSEQ_END:
1238 case ISD::EXTRACT_ELEMENT:
1239 case ISD::FLT_ROUNDS_:
1240 case ISD::SADDO:
1241 case ISD::SSUBO:
1242 case ISD::UADDO:
1243 case ISD::USUBO:
1244 case ISD::SMULO:
1245 case ISD::UMULO:
1246 case ISD::FPOWI:
1247 case ISD::MERGE_VALUES:
1248 case ISD::EH_RETURN:
1249 case ISD::FRAME_TO_ARGS_OFFSET:
1250 case ISD::EH_SJLJ_SETJMP:
1251 case ISD::EH_SJLJ_LONGJMP:
1258 case ISD::INIT_TRAMPOLINE:
1259 case ISD::ADJUST_TRAMPOLINE:
1260 case ISD::FRAMEADDR:
1261 case ISD::RETURNADDR:
1268 case ISD::READ_REGISTER:
1269 case ISD::WRITE_REGISTER:
1275 case ISD::DEBUGTRAP:
1278 // replace ISD::DEBUGTRAP with ISD::TRAP
1280 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1289 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1301 case ISD::SHL:
1302 case ISD::SRL:
1303 case ISD::SRA:
1304 case ISD::ROTL:
1305 case ISD::ROTR:
1318 case ISD::SRL_PARTS:
1319 case ISD::SRA_PARTS:
1320 case ISD::SHL_PARTS:
1386 case ISD::CALLSEQ_START:
1387 case ISD::CALLSEQ_END:
1389 case ISD::LOAD: {
1392 case ISD::STORE: {
1439 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1443 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1448 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1478 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1482 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1512 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1517 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1535 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1556 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1577 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1587 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1595 ISD::SETLT);
1597 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1601 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1627 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1629 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1665 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1673 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1679 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1683 case ISD::SETO:
1684 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1687 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1688 case ISD::SETUO:
1689 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1692 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1693 case ISD::SETOEQ:
1694 case ISD::SETOGT:
1695 case ISD::SETOGE:
1696 case ISD::SETOLT:
1697 case ISD::SETOLE:
1698 case ISD::SETONE:
1699 case ISD::SETUEQ:
1700 case ISD::SETUNE:
1701 case ISD::SETUGT:
1702 case ISD::SETUGE:
1703 case ISD::SETULT:
1704 case ISD::SETULE:
1709 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1710 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1711 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1715 case ISD::SETLE:
1716 case ISD::SETGT:
1717 case ISD::SETGE:
1718 case ISD::SETLT:
1722 case ISD::SETNE:
1723 case ISD::SETEQ:
1725 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1737 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1799 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1841 if (V.getOpcode() == ISD::UNDEF)
1846 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1932 if (V.getOpcode() == ISD::UNDEF)
1953 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1975 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1990 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2000 if (V.getOpcode() == ISD::UNDEF)
2006 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2009 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2196 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2199 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2201 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2224 bool isSigned = Opcode == ISD::SDIVREM;
2312 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2313 ? ISD::FCOS : ISD::FSIN;
2322 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2412 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2422 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2445 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2453 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2456 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2477 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2479 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2480 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2481 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2482 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2483 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2485 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2494 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2498 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2500 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2501 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2503 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2504 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2511 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2517 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2519 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2521 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2524 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2528 ISD::SETUGE);
2532 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2534 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2535 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2538 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2539 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2540 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2541 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2542 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2546 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2550 ISD::SETLT);
2572 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2580 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2589 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2612 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2613 OpToUse = ISD::SINT_TO_FP;
2619 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2620 OpToUse = ISD::UINT_TO_FP;
2630 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2655 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2656 OpToUse = ISD::FP_TO_SINT;
2661 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2662 OpToUse = ISD::FP_TO_UINT;
2675 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2687 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2688 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2689 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2691 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2692 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2693 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2694 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2695 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2696 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2697 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2698 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2699 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2701 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2702 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2703 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2704 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2705 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2706 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2707 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2708 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2709 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2710 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2711 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2712 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2713 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2714 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2715 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2716 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2717 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2718 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2719 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2720 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2721 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2731 case ISD::CTPOP: {
2748 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2749 DAG.getNode(ISD::AND, dl, VT,
2750 DAG.getNode(ISD::SRL, dl, VT, Op,
2754 Op = DAG.getNode(ISD::ADD, dl, VT,
2755 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2756 DAG.getNode(ISD::AND, dl, VT,
2757 DAG.getNode(ISD::SRL, dl, VT, Op,
2761 Op = DAG.getNode(ISD::AND, dl, VT,
2762 DAG.getNode(ISD::ADD, dl, VT, Op,
2763 DAG.getNode(ISD::SRL, dl, VT, Op,
2767 Op = DAG.getNode(ISD::SRL, dl, VT,
2768 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2773 case ISD::CTLZ_ZERO_UNDEF:
2775 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2776 case ISD::CTLZ: {
2791 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2792 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2795 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2797 case ISD::CTTZ_ZERO_UNDEF:
2799 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2800 case ISD::CTTZ: {
2806 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2808 DAG.getNode(ISD::SUB, dl, VT, Op,
2810 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2811 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2812 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2813 return DAG.getNode(ISD::SUB, dl, VT,
2815 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2816 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2829 case ISD::ATOMIC_SWAP:
2839 case ISD::ATOMIC_CMP_SWAP:
2849 case ISD::ATOMIC_LOAD_ADD:
2859 case ISD::ATOMIC_LOAD_SUB:
2869 case ISD::ATOMIC_LOAD_AND:
2879 case ISD::ATOMIC_LOAD_OR:
2889 case ISD::ATOMIC_LOAD_XOR:
2899 case ISD::ATOMIC_LOAD_NAND:
2909 case ISD::ATOMIC_LOAD_MAX:
2919 case ISD::ATOMIC_LOAD_UMAX:
2929 case ISD::ATOMIC_LOAD_MIN:
2939 case ISD::ATOMIC_LOAD_UMIN:
2960 case ISD::CTPOP:
2961 case ISD::CTLZ:
2962 case ISD::CTLZ_ZERO_UNDEF:
2963 case ISD::CTTZ:
2964 case ISD::CTTZ_ZERO_UNDEF:
2968 case ISD::BSWAP:
2971 case ISD::FRAMEADDR:
2972 case ISD::RETURNADDR:
2973 case ISD::FRAME_TO_ARGS_OFFSET:
2976 case ISD::FLT_ROUNDS_:
2979 case ISD::EH_RETURN:
2980 case ISD::EH_LABEL:
2981 case ISD::PREFETCH:
2982 case ISD::VAEND:
2983 case ISD::EH_SJLJ_LONGJMP:
2988 case ISD::EH_SJLJ_SETJMP:
2994 case ISD::ATOMIC_FENCE: {
3010 case ISD::ATOMIC_LOAD: {
3015 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3025 case ISD::ATOMIC_STORE: {
3027 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3040 case ISD::ATOMIC_SWAP:
3041 case ISD::ATOMIC_LOAD_ADD:
3042 case ISD::ATOMIC_LOAD_SUB:
3043 case ISD::ATOMIC_LOAD_AND:
3044 case ISD::ATOMIC_LOAD_OR:
3045 case ISD::ATOMIC_LOAD_XOR:
3046 case ISD::ATOMIC_LOAD_NAND:
3047 case ISD::ATOMIC_LOAD_MIN:
3048 case ISD::ATOMIC_LOAD_MAX:
3049 case ISD::ATOMIC_LOAD_UMIN:
3050 case ISD::ATOMIC_LOAD_UMAX:
3051 case ISD::ATOMIC_CMP_SWAP: {
3057 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3063 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3071 Res, Node->getOperand(2), ISD::SETEQ);
3078 case ISD::DYNAMIC_STACKALLOC:
3081 case ISD::MERGE_VALUES:
3085 case ISD::UNDEF: {
3095 case ISD::TRAP: {
3108 case ISD::FP_ROUND:
3109 case ISD::BITCAST:
3114 case ISD::FP_EXTEND:
3120 case ISD::SIGN_EXTEND_INREG: {
3131 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3133 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3137 case ISD::FP_ROUND_INREG: {
3150 case ISD::SINT_TO_FP:
3151 case ISD::UINT_TO_FP:
3152 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3156 case ISD::FP_TO_SINT: {
3177 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
3179 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
3180 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
3182 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
3184 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
3185 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
3189 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
3190 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
3197 DAG.getNode(ISD::SHL, dl, NVT, R,
3199 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3201 DAG.getNode(ISD::SRL, dl, NVT, R,
3203 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3205 ISD::SETGT);
3207 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3208 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3212 DAG.getConstant(0, NVT), Ret, ISD::SETLT));
3215 case ISD::FP_TO_UINT: {
3226 Tmp1, ISD::SETLT);
3227 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3228 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3229 DAG.getNode(ISD::FSUB, dl, VT,
3231 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3237 case ISD::VAARG: {
3252 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3256 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3262 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3275 case ISD::VACOPY: {
3288 case ISD::EXTRACT_VECTOR_ELT:
3291 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3297 case ISD::EXTRACT_SUBVECTOR:
3300 case ISD::INSERT_SUBVECTOR:
3303 case ISD::CONCAT_VECTORS: {
3307 case ISD::SCALAR_TO_VECTOR:
3310 case ISD::INSERT_VECTOR_ELT:
3315 case ISD::VECTOR_SHUFFLE: {
3343 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3344 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3377 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3381 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3387 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3389 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3393 case ISD::EXTRACT_ELEMENT: {
3397 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3400 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3403 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3409 case ISD::STACKSAVE:
3421 case ISD::STACKRESTORE:
3431 case ISD::FCOPYSIGN:
3434 case ISD::FNEG:
3437 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3441 case ISD::FABS: {
3447 Tmp1, Tmp2, ISD::SETUGT);
3448 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3453 case ISD::FSQRT:
3458 case ISD::FSIN:
3459 case ISD::FCOS: {
3461 bool isSIN = Node->getOpcode() == ISD::FSIN;
3462 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3464 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3468 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3483 case ISD::FSINCOS:
3487 case ISD::FLOG:
3492 case ISD::FLOG2:
3497 case ISD::FLOG10:
3502 case ISD::FEXP:
3507 case ISD::FEXP2:
3512 case ISD::FTRUNC:
3517 case ISD::FFLOOR:
3522 case ISD::FCEIL:
3527 case ISD::FRINT:
3532 case ISD::FNEARBYINT:
3539 case ISD::FROUND:
3546 case ISD::FPOWI:
3551 case ISD::FPOW:
3556 case ISD::FDIV:
3561 case ISD::FREM:
3566 case ISD::FMA:
3571 case ISD::FP16_TO_FP32:
3574 case ISD::FP32_TO_FP16:
3577 case ISD::ConstantFP: {
3585 case ISD::FSUB: {
3587 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3588 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3590 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3591 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3595 case ISD::SUB: {
3597 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3598 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3600 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3602 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3603 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3606 case ISD::UREM:
3607 case ISD::SREM: {
3609 bool isSigned = Node->getOpcode() == ISD::SREM;
3610 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3611 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3624 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3625 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3639 case ISD::UDIV:
3640 case ISD::SDIV: {
3641 bool isSigned = Node->getOpcode() == ISD::SDIV;
3642 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3663 case ISD::MULHU:
3664 case ISD::MULHS: {
3665 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3666 ISD::SMUL_LOHI;
3676 case ISD::SDIVREM:
3677 case ISD::UDIVREM:
3681 case ISD::MUL: {
3689 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3690 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3691 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3692 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3695 OpToUse = ISD::SMUL_LOHI;
3697 OpToUse = ISD::UMUL_LOHI;
3699 OpToUse = ISD::SMUL_LOHI;
3701 OpToUse = ISD::UMUL_LOHI;
3711 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3712 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3713 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3714 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3716 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3717 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3720 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3721 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3732 case ISD::SADDO:
3733 case ISD::SSUBO: {
3736 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3737 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3754 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3755 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3757 Node->getOpcode() == ISD::SADDO ?
3758 ISD::SETEQ : ISD::SETNE);
3760 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3761 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3763 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3767 case ISD::UADDO:
3768 case ISD::USUBO: {
3771 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3772 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3778 ISD::CondCode CC
3779 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3785 case ISD::UMULO:
3786 case ISD::SMULO: {
3794 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3795 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3796 bool isSigned = Node->getOpcode() == ISD::SMULO;
3798 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3807 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3808 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3810 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3831 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3833 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3842 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3844 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3855 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3857 ISD::SETNE);
3860 DAG.getConstant(0, VT), ISD::SETNE);
3866 case ISD::BUILD_PAIR: {
3868 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3869 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3870 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3873 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3876 case ISD::SELECT:
3880 if (Tmp1.getOpcode() == ISD::SETCC) {
3887 Tmp2, Tmp3, ISD::SETNE);
3891 case ISD::BR_JT: {
3902 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3904 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3908 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3916 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3919 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3923 case ISD::BRCOND:
3928 if (Tmp2.getOpcode() == ISD::SETCC) {
3929 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3935 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3936 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3938 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3939 DAG.getCondCode(ISD::SETNE), Tmp3,
3945 case ISD::SETCC: {
3956 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3981 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3987 case ISD::SELECT_CC: {
3994 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
4000 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
4001 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
4004 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
4014 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
4023 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
4047 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
4051 CC = DAG.getCondCode(ISD::SETNE);
4052 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
4059 case ISD::BR_CC: {
4078 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4082 Tmp4 = DAG.getCondCode(ISD::SETNE);
4083 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4089 case ISD::BUILD_VECTOR:
4092 case ISD::SRA:
4093 case ISD::SRL:
4094 case ISD::SHL: {
4103 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4107 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4115 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4119 case ISD::GLOBAL_OFFSET_TABLE:
4120 case ISD::GlobalAddress:
4121 case ISD::GlobalTLSAddress:
4122 case ISD::ExternalSymbol:
4123 case ISD::ConstantPool:
4124 case ISD::JumpTable:
4125 case ISD::INTRINSIC_W_CHAIN:
4126 case ISD::INTRINSIC_WO_CHAIN:
4127 case ISD::INTRINSIC_VOID:
4140 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4141 Node->getOpcode() == ISD::SINT_TO_FP ||
4142 Node->getOpcode() == ISD::SETCC) {
4149 case ISD::CTTZ:
4150 case ISD::CTTZ_ZERO_UNDEF:
4151 case ISD::CTLZ:
4152 case ISD::CTLZ_ZERO_UNDEF:
4153 case ISD::CTPOP:
4155 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4159 if (Node->getOpcode() == ISD::CTTZ) {
4163 ISD::SETEQ);
4166 } else if (Node->getOpcode() == ISD::CTLZ ||
4167 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4169 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4173 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4175 case ISD::BSWAP: {
4177 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4178 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4179 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4184 case ISD::FP_TO_UINT:
4185 case ISD::FP_TO_SINT:
4187 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4190 case ISD::UINT_TO_FP:
4191 case ISD::SINT_TO_FP:
4193 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4196 case ISD::VAARG: {
4202 TruncOp = ISD::BITCAST;
4206 TruncOp = ISD::TRUNCATE;
4223 case ISD::AND:
4224 case ISD::OR:
4225 case ISD::XOR: {
4228 ExtOp = ISD::BITCAST;
4229 TruncOp = ISD::BITCAST;
4232 ExtOp = ISD::ANY_EXTEND;
4233 TruncOp = ISD::TRUNCATE;
4243 case ISD::SELECT: {
4247 ExtOp = ISD::BITCAST;
4248 TruncOp = ISD::BITCAST;
4250 ExtOp = ISD::ANY_EXTEND;
4251 TruncOp = ISD::TRUNCATE;
4253 ExtOp = ISD::FP_EXTEND;
4254 TruncOp = ISD::FP_ROUND;
4262 if (TruncOp != ISD::FP_ROUND)
4270 case ISD::VECTOR_SHUFFLE: {
4274 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4275 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4279 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4283 case ISD::SETCC: {
4284 unsigned ExtOp = ISD::FP_EXTEND;
4286 ISD::CondCode CCCode =
4288 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4292 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4296 case ISD::FDIV:
4297 case ISD::FREM:
4298 case ISD::FPOW: {
4299 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4300 ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4302 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4306 case ISD::FLOG2:
4307 case ISD::FEXP2:
4308 case ISD::FLOG:
4309 case ISD::FEXP: {
4310 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4312 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
