Lines Matching refs:ISD
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
69 case ISD::ANY_EXTEND:
70 case ISD::BSWAP:
71 case ISD::CTLZ:
72 case ISD::CTLZ_ZERO_UNDEF:
73 case ISD::CTPOP:
74 case ISD::CTTZ:
75 case ISD::CTTZ_ZERO_UNDEF:
76 case ISD::FABS:
77 case ISD::FCEIL:
78 case ISD::FCOS:
79 case ISD::FEXP:
80 case ISD::FEXP2:
81 case ISD::FFLOOR:
82 case ISD::FLOG:
83 case ISD::FLOG10:
84 case ISD::FLOG2:
85 case ISD::FNEARBYINT:
86 case ISD::FNEG:
87 case ISD::FP_EXTEND:
88 case ISD::FP_TO_SINT:
89 case ISD::FP_TO_UINT:
90 case ISD::FRINT:
91 case ISD::FROUND:
92 case ISD::FSIN:
93 case ISD::FSQRT:
94 case ISD::FTRUNC:
95 case ISD::SIGN_EXTEND:
96 case ISD::SINT_TO_FP:
97 case ISD::TRUNCATE:
98 case ISD::UINT_TO_FP:
99 case ISD::ZERO_EXTEND:
103 case ISD::ADD:
104 case ISD::AND:
105 case ISD::FADD:
106 case ISD::FCOPYSIGN:
107 case ISD::FDIV:
108 case ISD::FMUL:
109 case ISD::FPOW:
110 case ISD::FREM:
111 case ISD::FSUB:
112 case ISD::MUL:
113 case ISD::OR:
114 case ISD::SDIV:
115 case ISD::SREM:
116 case ISD::SUB:
117 case ISD::UDIV:
118 case ISD::UREM:
119 case ISD::XOR:
120 case ISD::SHL:
121 case ISD::SRA:
122 case ISD::SRL:
125 case ISD::FMA:
158 return DAG.getNode(ISD::BITCAST, SDLoc(N),
168 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
184 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
192 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
198 return DAG.getNode(ISD::FPOWI, SDLoc(N),
209 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
255 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
274 if (Cond->getOpcode() == ISD::SETCC) {
291 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
298 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
336 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
346 if (Arg.getOpcode() == ISD::UNDEF)
368 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
370 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
375 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
379 ISD::NodeType ExtendCode =
404 case ISD::BITCAST:
407 case ISD::ANY_EXTEND:
408 case ISD::ZERO_EXTEND:
409 case ISD::SIGN_EXTEND:
410 case ISD::TRUNCATE:
413 case ISD::CONCAT_VECTORS:
416 case ISD::EXTRACT_VECTOR_ELT:
419 case ISD::VSELECT:
422 case ISD::STORE:
425 case ISD::FP_ROUND:
450 return DAG.getNode(ISD::BITCAST, SDLoc(N),
464 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
473 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
482 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
489 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
495 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
524 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
527 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
559 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
560 case ISD::VSELECT:
561 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
562 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
563 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
564 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
565 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
566 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
567 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
568 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
569 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
570 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
571 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
572 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
573 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
574 case ISD::LOAD:
577 case ISD::SETCC:
580 case ISD::VECTOR_SHUFFLE:
584 case ISD::BSWAP:
585 case ISD::CONVERT_RNDSAT:
586 case ISD::CTLZ:
587 case ISD::CTTZ:
588 case ISD::CTLZ_ZERO_UNDEF:
589 case ISD::CTTZ_ZERO_UNDEF:
590 case ISD::CTPOP:
591 case ISD::FABS:
592 case ISD::FCEIL:
593 case ISD::FCOS:
594 case ISD::FEXP:
595 case ISD::FEXP2:
596 case ISD::FFLOOR:
597 case ISD::FLOG:
598 case ISD::FLOG10:
599 case ISD::FLOG2:
600 case ISD::FNEARBYINT:
601 case ISD::FNEG:
602 case ISD::FP_EXTEND:
603 case ISD::FP_ROUND:
604 case ISD::FP_TO_SINT:
605 case ISD::FP_TO_UINT:
606 case ISD::FRINT:
607 case ISD::FROUND:
608 case ISD::FSIN:
609 case ISD::FSQRT:
610 case ISD::FTRUNC:
611 case ISD::SINT_TO_FP:
612 case ISD::TRUNCATE:
613 case ISD::UINT_TO_FP:
617 case ISD::ANY_EXTEND:
618 case ISD::SIGN_EXTEND:
619 case ISD::ZERO_EXTEND:
623 case ISD::ADD:
624 case ISD::SUB:
625 case ISD::MUL:
626 case ISD::FADD:
627 case ISD::FCOPYSIGN:
628 case ISD::FSUB:
629 case ISD::FMUL:
630 case ISD::SDIV:
631 case ISD::UDIV:
632 case ISD::FDIV:
633 case ISD::FPOW:
634 case ISD::AND:
635 case ISD::OR:
636 case ISD::XOR:
637 case ISD::SHL:
638 case ISD::SRA:
639 case ISD::SRL:
640 case ISD::UREM:
641 case ISD::SREM:
642 case ISD::FREM:
645 case ISD::FMA:
711 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
712 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
720 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
721 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
735 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
736 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
746 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
749 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
767 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
770 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
782 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
784 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
818 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
830 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
831 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
862 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
865 ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
893 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
906 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
912 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
917 ISD::LoadExtType ExtType = LD->getExtensionType();
931 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
936 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
938 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
945 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
986 if (N->getOpcode() == ISD::FP_ROUND) {
989 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
996 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1145 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1151 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1198 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1199 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1200 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1201 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1202 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1203 case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break;
1204 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1205 case ISD::STORE:
1208 case ISD::VSELECT:
1211 case ISD::CTTZ:
1212 case ISD::CTLZ:
1213 case ISD::CTPOP:
1214 case ISD::FP_EXTEND:
1215 case ISD::FP_TO_SINT:
1216 case ISD::FP_TO_UINT:
1217 case ISD::SINT_TO_FP:
1218 case ISD::UINT_TO_FP:
1219 case ISD::FTRUNC:
1220 case ISD::SIGN_EXTEND:
1221 case ISD::ZERO_EXTEND:
1222 case ISD::ANY_EXTEND:
1270 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1272 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1274 ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1291 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1306 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1324 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1326 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1361 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1394 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1406 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1423 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1429 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1475 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec);
1476 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);
1479 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1485 return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1501 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1502 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1503 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1519 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1520 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1522 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1550 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1551 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1552 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1553 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1554 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1555 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1556 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1557 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1558 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1559 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1560 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1561 case ISD::VSELECT:
1562 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1563 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1564 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1565 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1566 case ISD::VECTOR_SHUFFLE:
1570 case ISD::ADD:
1571 case ISD::AND:
1572 case ISD::MUL:
1573 case ISD::MULHS:
1574 case ISD::MULHU:
1575 case ISD::OR:
1576 case ISD::SUB:
1577 case ISD::XOR:
1581 case ISD::FADD:
1582 case ISD::FCOPYSIGN:
1583 case ISD::FMUL:
1584 case ISD::FPOW:
1585 case ISD::FSUB:
1586 case ISD::FDIV:
1587 case ISD::FREM:
1588 case ISD::SDIV:
1589 case ISD::UDIV:
1590 case ISD::SREM:
1591 case ISD::UREM:
1595 case ISD::FPOWI:
1599 case ISD::SHL:
1600 case ISD::SRA:
1601 case ISD::SRL:
1605 case ISD::ANY_EXTEND:
1606 case ISD::FP_EXTEND:
1607 case ISD::FP_ROUND:
1608 case ISD::FP_TO_SINT:
1609 case ISD::FP_TO_UINT:
1610 case ISD::SIGN_EXTEND:
1611 case ISD::SINT_TO_FP:
1612 case ISD::TRUNCATE:
1613 case ISD::UINT_TO_FP:
1614 case ISD::ZERO_EXTEND:
1618 case ISD::BSWAP:
1619 case ISD::CTLZ:
1620 case ISD::CTPOP:
1621 case ISD::CTTZ:
1622 case ISD::FABS:
1623 case ISD::FCEIL:
1624 case ISD::FCOS:
1625 case ISD::FEXP:
1626 case ISD::FEXP2:
1627 case ISD::FFLOOR:
1628 case ISD::FLOG:
1629 case ISD::FLOG10:
1630 case ISD::FLOG2:
1631 case ISD::FNEARBYINT:
1632 case ISD::FNEG:
1633 case ISD::FRINT:
1634 case ISD::FROUND:
1635 case ISD::FSIN:
1636 case ISD::FSQRT:
1637 case ISD::FTRUNC:
1640 case ISD::FMA:
1710 SDValue EOp1 = DAG.getNode(ISD
1712 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1725 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1728 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1767 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1785 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1805 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
1848 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
1855 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1871 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1883 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
1957 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1972 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2007 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2009 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2010 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2034 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2057 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2065 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2097 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2103 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2121 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2148 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2155 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2171 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2181 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2205 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2214 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2220 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2225 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2232 ISD::LoadExtType ExtType = LD->getExtensionType();
2236 if (ExtType != ISD::NON_EXTLOAD)
2248 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2259 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2301 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2315 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2370 return DAG.getNode(ISD::SETCC, SDLoc(N),
2397 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2398 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2399 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2400 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2401 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2402 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2404 case ISD::ANY_EXTEND:
2405 case ISD::SIGN_EXTEND:
2406 case ISD::ZERO_EXTEND:
2410 case ISD::FP_EXTEND:
2411 case ISD::FP_TO_SINT:
2412 case ISD::FP_TO_UINT:
2413 case ISD::SINT_TO_FP:
2414 case ISD::UINT_TO_FP:
2415 case ISD::TRUNCATE:
2467 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2471 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2489 case ISD::ANY_EXTEND:
2491 case ISD::SIGN_EXTEND:
2493 case ISD::ZERO_EXTEND:
2516 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2519 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2536 ISD::BITCAST, dl, NewVT, InOp);
2537 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2565 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2568 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2573 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2579 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2597 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
2612 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
2619 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2702 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2709 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2714 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2717 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2759 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2760 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2772 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
2785 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2806 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
2849 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2858 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2872 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
2878 ISD::LoadExtType ExtType) {
2908 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2923 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2959 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2968 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2975 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2979 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2987 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3025 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3033 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3036 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3069 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3073 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3082 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3088 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
