Lines Matching refs:ISD
119 ISD::CondCode &CCCode,
127 case ISD::SETEQ:
128 case ISD::SETOEQ:
132 case ISD::SETNE:
133 case ISD::SETUNE:
137 case ISD::SETGE:
138 case ISD::SETOGE:
142 case ISD::SETLT:
143 case ISD::SETOLT:
147 case ISD::SETLE:
148 case ISD::SETOLE:
152 case ISD::SETGT:
153 case ISD::SETOGT:
157 case ISD::SETUO:
161 case ISD::SETO:
169 case ISD::SETONE:
174 case ISD::SETUGT:
178 case ISD::SETUGE:
182 case ISD::SETULT:
186 case ISD::SETULE:
190 case ISD::SETUEQ:
206 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
211 NewLHS = DAG.getNode(ISD::SETCC, dl,
214 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
286 // FIXME: ISD::SELECT, ISD::SELECT_CC
289 case ISD::XOR:
290 case ISD::AND:
291 case ISD::OR: {
295 if (Op.getOpcode() == ISD::XOR &&
352 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
354 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
357 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
400 if (Op.getOpcode() != ISD::UNDEF)
409 case ISD::Constant:
414 case ISD::AND:
462 case ISD::OR:
496 case ISD::XOR:
520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
538 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
566 case ISD::SELECT:
584 case ISD::SELECT_CC:
602 case ISD::SHL:
614 if (InOp.getOpcode() == ISD::SRL &&
618 unsigned Opc = ISD::SHL;
622 Opc = ISD::SRL;
639 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
644 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
649 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
653 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
662 InnerOp.getOpcode() == ISD::SRL &&
675 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
677 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
689 case ISD::SRL:
703 if (InOp.getOpcode() == ISD::SHL &&
707 unsigned Opc = ISD::SRL;
711 Opc = ISD::SHL;
733 case ISD::SRA:
740 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
772 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
782 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
791 case ISD::SIGN_EXTEND_INREG: {
807 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
854 case ISD::BUILD_PAIR: {
879 case ISD::ZERO_EXTEND: {
888 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
901 case ISD::SIGN_EXTEND: {
910 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
928 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
942 case ISD::ANY_EXTEND: {
954 case ISD::TRUNCATE: {
972 case ISD::SRL:
976 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
997 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1000 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1012 case ISD::AssertZext: {
1026 case ISD::BITCAST:
1034 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1035 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1040 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1043 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1046 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1052 case ISD::ADD:
1053 case ISD::MUL:
1054 case ISD::SUB: {
1092 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1093 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1094 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1095 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1107 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1108 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1109 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1110 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1123 if (Val.getOpcode() == ISD::SHL)
1131 if (Val.getOpcode() == ISD::SRL)
1207 ISD::CondCode Cond, bool foldBooleans,
1214 case ISD::SETFALSE:
1215 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1216 case ISD::SETTRUE:
1217 case ISD::SETTRUE2: {
1227 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1239 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1240 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1241 N0.getOperand(1).getOpcode() == ISD::Constant) {
1244 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1246 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1249 Cond = ISD::SETNE;
1253 Cond = ISD::SETEQ;
1263 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1266 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1274 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1275 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1277 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1278 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1287 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1290 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1294 } else if (N0->getOpcode() == ISD::AND) {
1303 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1313 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1315 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1326 !ISD::isSignedIntSetCC(Cond) &&
1327 N0.getOpcode() == ISD::AND && C1 == 0 &&
1340 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1366 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1373 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1382 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1390 case ISD::SETUGT:
1391 case ISD::SETUGE:
1392 case ISD::SETEQ: return DAG.getConstant(0, VT);
1393 case ISD::SETULT:
1394 case ISD::SETULE:
1395 case ISD::SETNE: return DAG.getConstant(1, VT);
1396 case ISD::SETGT:
1397 case ISD::SETGE:
1400 case ISD::SETLT:
1401 case ISD::SETLE:
1411 case ISD::SETEQ:
1412 case ISD::SETNE:
1413 case ISD::SETUGT:
1414 case ISD::SETUGE:
1415 case ISD::SETULT:
1416 case ISD::SETULE: {
1419 (isOperationLegal(ISD::SETCC, newVT) &&
1433 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1434 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1443 return DAG.getConstant(Cond == ISD::SETNE, VT);
1451 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1464 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1466 if (N0.getOpcode() == ISD::SETCC &&
1468 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1470 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1472 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1473 CC = ISD::getSetCCInverse(CC,
1480 if ((N0.getOpcode() == ISD::XOR ||
1481 (N0.getOpcode() == ISD::AND &&
1482 N0.getOperand(0).getOpcode() == ISD::XOR &&
1494 if (N0.getOpcode() == ISD::XOR)
1497 assert(N0.getOpcode() == ISD::AND &&
1498 N0.getOperand(0).getOpcode() == ISD::XOR);
1500 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1506 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1513 if (Op0.getOpcode() == ISD::TRUNCATE)
1516 if ((Op0.getOpcode() == ISD::XOR) &&
1517 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1518 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1520 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1524 if (Op0.getOpcode() == ISD::AND &&
1529 Op0 = DAG.getNode(ISD::AND, dl, VT,
1530 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1533 Op0 = DAG.getNode(ISD::AND, dl, VT,
1534 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1539 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1541 if (Op0.getOpcode() == ISD::AssertZext &&
1545 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1551 if (ISD::isSignedIntSetCC(Cond)) {
1560 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1564 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1575 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1579 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1590 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1592 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1594 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1596 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1600 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1601 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1603 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1604 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1607 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1610 ISD::SETEQ);
1612 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1615 ISD::SETEQ);
1621 if (Cond == ISD::SETUGT &&
1625 ISD::SETLT);
1628 if (Cond == ISD::SETULT &&
1633 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1637 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1640 N0.getOpcode() == ISD::AND)
1645 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1648 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1649 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1652 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1656 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1657 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1666 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1667 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1676 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1682 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1683 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1684 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1691 ISD::CondCode NewCond = Cond;
1695 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1704 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1722 switch (ISD::getUnorderedFlavor(Cond)) {
1737 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1748 if (Cond == ISD::SETOEQ &&
1749 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1750 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1751 if (Cond == ISD::SETUEQ &&
1752 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1753 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1754 if (Cond == ISD::SETUNE &&
1755 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1756 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1757 if (Cond == ISD::SETONE &&
1758 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1759 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1761 if (Cond == ISD::SETOEQ &&
1762 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1763 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1764 if (Cond == ISD::SETUEQ &&
1765 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1766 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1767 if (Cond == ISD::SETUNE &&
1768 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1769 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1770 if (Cond == ISD::SETONE &&
1771 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1772 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1785 EqVal = ISD::isTrueWhenEqual(Cond);
1788 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1796 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1799 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1803 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1809 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1811 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1812 N0.getOpcode() == ISD::XOR) {
1837 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1845 if (N0.getOpcode() == ISD::XOR)
1859 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1887 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1889 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1899 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1900 N1.getOpcode() == ISD::XOR) {
1910 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1912 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1925 if (N0.getOpcode() == ISD::AND)
1928 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1936 if (N1.getOpcode() == ISD::AND)
1939 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1954 case ISD::SETEQ: // X == Y -> ~(X^Y)
1955 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1960 case ISD::SETNE: // X != Y --> (X^Y)
1961 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1963 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1964 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1966 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1970 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1971 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1973 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1977 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1978 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1980 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1984 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1985 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1987 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1994 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2014 if (N->getOpcode() == ISD::ADD) {
2112 if (Op.getOpcode() == ISD::BasicBlock) {
2127 if (Op.getOpcode() == ISD::ADD) {
2628 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2639 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2642 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2662 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2663 isOperationLegalOrCustom(ISD::MULHS, VT))
2664 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2666 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2667 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2668 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2675 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2681 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2687 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2693 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2698 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2701 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2726 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2738 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2739 isOperationLegalOrCustom(ISD::MULHU, VT))
2740 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2741 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2742 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2743 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2753 return DAG.getNode(ISD::SRL, dl, VT, Q,
2756 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2759 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2763 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2766 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2792 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2793 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2794 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2795 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2807 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2808 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2809 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2821 Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2828 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2829 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2837 Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2844 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2845 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2851 isOperationLegalOrCustom(ISD::SRL, VT) &&
2852 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2855 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2856 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2857 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2858 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2866 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2870 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2871 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2872 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2873 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2877 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2878 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2879 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2880 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2881 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2882 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
