Lines Matching refs:ResultReg
125 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
186 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
188 ResultReg)
192 return ResultReg;
217 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
220 return ResultReg;
235 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
239 return ResultReg;
259 unsigned ResultReg;
267 ResultReg = createResultReg(&AArch64::GPR64RegClass);
269 ResultReg)
278 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
280 ResultReg)
285 return ResultReg;
470 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
472 ResultReg)
477 Addr.setReg(ResultReg);
484 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
486 if (ResultReg == 0)
488 Addr.setReg(ResultReg);
515 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
568 return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
578 ResultReg = createResultReg(RC);
580 TII.get(Opc), ResultReg);
585 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
589 .addReg(ResultReg)
591 ResultReg = ANDReg;
609 unsigned ResultReg;
610 if (!EmitLoad(VT, ResultReg, Addr))
613 UpdateValueMap(I, ResultReg);
1009 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1011 ResultReg)
1016 UpdateValueMap(I, ResultReg);
1074 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1076 ResultReg)
1081 UpdateValueMap(I, ResultReg);
1094 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1096 ResultReg).addReg(Op);
1097 UpdateValueMap(I, ResultReg);
1110 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
1112 ResultReg).addReg(Op);
1113 UpdateValueMap(I, ResultReg);
1143 unsigned ResultReg = createResultReg(
1145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1147 UpdateValueMap(I, ResultReg);
1188 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1191 UpdateValueMap(I, ResultReg);
1295 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1298 ResultReg).addReg(RVLocs[0].getLocReg());
1302 UpdateValueMap(I, ResultReg);
1468 unsigned ResultReg;
1469 RV = EmitLoad(VT, ResultReg, Src);
1473 RV = EmitStore(VT, ResultReg, Dest);
1717 unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass);
1719 ResultReg)
1730 .addReg(ResultReg)
1732 ResultReg = Reg64;
1734 return ResultReg;
1740 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1742 ResultReg)
1746 return ResultReg;
1806 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1807 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1812 return ResultReg;
1837 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
1838 if (ResultReg == 0)
1840 UpdateValueMap(I, ResultReg);
1880 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1881 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
1885 UpdateValueMap(I, ResultReg);
1927 unsigned ResultReg = createResultReg(TLI.getRegClassFor(SrcVT));
1928 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1932 UpdateValueMap(I, ResultReg);
