Lines Matching refs:EXTR
56 // Place holder until extr generation is tested fully.
58 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
688 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
6453 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6472 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6475 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6501 // not really an EXTR.
6513 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6566 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
