Lines Matching refs:SETCC
81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
519 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
1526 case ISD::SETCC:
3099 "Unexpected setcc expansion!");
3110 // the true and false operands here. This will allow the setcc to be
3129 // the true and false operands here. This will allow the setcc to be
3199 if (CC.getOpcode() == ISD::SETCC)
6819 /// \brief Helper structure to keep track of SetCC information.
6825 /// \brief Helper structure to be able to read SetCC information. If set to
6840 // If this is a setcc, this is straight forward.
6841 if (Op.getOpcode() == ISD::SETCC) {
6881 // Returns true if Op is setcc or zext of setcc.
6890 // (add x, [zext] (setcc cc ...) )
7636 // vselect (v1i1 setcc) ->
7637 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7645 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7658 SDValue SetCC =
7662 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7666 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7668 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7677 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7693 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7697 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
