Lines Matching refs:f128
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
157 // Virtually no operation on f128 is legal, but LLVM can't expand them when
159 setOperationAction(ISD::FABS, MVT::f128, Expand);
160 setOperationAction(ISD::FADD, MVT::f128, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
162 setOperationAction(ISD::FCOS, MVT::f128, Expand);
163 setOperationAction(ISD::FDIV, MVT::f128, Custom);
164 setOperationAction(ISD::FMA, MVT::f128, Expand);
165 setOperationAction(ISD::FMUL, MVT::f128, Custom);
166 setOperationAction(ISD::FNEG, MVT::f128, Expand);
167 setOperationAction(ISD::FPOW, MVT::f128, Expand);
168 setOperationAction(ISD::FREM, MVT::f128, Expand);
169 setOperationAction(ISD::FRINT, MVT::f128, Expand);
170 setOperationAction(ISD::FSIN, MVT::f128, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
172 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
173 setOperationAction(ISD::FSUB, MVT::f128, Custom);
174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
177 setOperationAction(ISD::SELECT, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
181 // Lowering for many of the conversions is actually specified by the non-f128
182 // type. The LowerXXX function will be trivial when f128 isn't involved.
315 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
1202 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1359 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1369 if (Op.getOperand(0).getValueType() != MVT::f128) {
1370 // It's legal except when f128 is involved
1415 if (Op.getOperand(0).getValueType() != MVT::f128) {
1416 // It's legal except when f128 is involved
1473 if (Op.getValueType() != MVT::f128)
1722 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1892 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2840 // Handle f128 first, since lowering it will result in comparing the return
2843 if (LHS.getValueType() == MVT::f128) {
2844 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3091 // Handle f128 first, since one possible outcome is a normal integer
3093 if (LHS.getValueType() == MVT::f128) {
3094 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3216 // Handle f128 first, because it will result in a comparison of some RTLIB
3218 if (LHS.getValueType() == MVT::f128) {
3219 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3790 // FIXME: We should be able to handle f128 as well with a clever lowering.
6167 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6168 return MVT::f128;
