Lines Matching refs:Op0
110 unsigned Op0, bool Op0IsKill);
113 unsigned Op0, bool Op0IsKill,
117 unsigned Op0, bool Op0IsKill,
122 unsigned Op0, bool Op0IsKill,
126 unsigned Op0, bool Op0IsKill,
288 unsigned Op0, bool Op0IsKill) {
294 Op0 = constrainOperandRegClass(II, Op0, 1);
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
300 .addReg(Op0, Op0IsKill * RegState::Kill));
310 unsigned Op0, bool Op0IsKill,
317 Op0 = constrainOperandRegClass(II, Op0, 1);
323 .addReg(Op0, Op0IsKill * RegState::Kill)
327 .addReg(Op0, Op0IsKill * RegState::Kill)
338 unsigned Op0, bool Op0IsKill,
346 Op0 = constrainOperandRegClass(II, Op0, 1);
353 .addReg(Op0, Op0IsKill * RegState::Kill)
358 .addReg(Op0, Op0IsKill * RegState::Kill)
370 unsigned Op0, bool Op0IsKill,
377 Op0 = constrainOperandRegClass(II, Op0, 1);
381 .addReg(Op0, Op0IsKill * RegState::Kill)
385 .addReg(Op0, Op0IsKill * RegState::Kill)
396 unsigned Op0, bool Op0IsKill,
404 Op0 = constrainOperandRegClass(II, Op0, 1);
409 .addReg(Op0, Op0IsKill * RegState::Kill)
414 .addReg(Op0, Op0IsKill * RegState::Kill)
1174 Value *Op0 = I->getOperand(0);
1187 SrcReg = getRegForValue(Op0);
