Lines Matching refs:isZExt
172 bool isZExt);
174 unsigned Alignment = 0, bool isZExt = true,
183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
959 unsigned Alignment, bool isZExt, bool allocReg) {
971 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
973 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
975 if (isZExt) {
990 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
992 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
994 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1363 bool isZExt) {
1384 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1446 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1449 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1571 /*isZExt*/!isSigned);
1955 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1964 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
2126 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2127 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2591 bool isZExt) {
2676 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2678 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2734 bool isZExt = isa<ZExtInst>(I);
2746 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2886 uint8_t isZExt : 1;
2917 bool isZExt;
2924 isZExt = FoldableLoadExtends[i].isZExt;
2934 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
