Home | History | Annotate | Download | only in ARM

Lines Matching refs:INSERT_VECTOR_ELT

102   setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
561 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
1296 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1310 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
3008 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3010 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4984 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5015 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5034 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5085 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5098 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5561 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5595 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5599 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
6236 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8683 // i32, turn the build_vector into a sequence of insert_vector_elt.
8715 // => BITCAST INSERT_VECTOR_ELT
8716 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8734 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8743 /// ISD::INSERT_VECTOR_ELT.
8763 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
9638 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);