Lines Matching defs:NewOpc
7324 unsigned NewOpc;
7327 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7328 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7329 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7333 TmpInst.setOpcode(NewOpc);
7360 unsigned newOpc;
7363 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7364 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7365 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7366 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7368 TmpInst.setOpcode(newOpc);
7394 unsigned newOpc;
7397 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7398 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7399 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7400 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7401 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7405 TmpInst.setOpcode(newOpc);
7411 if (newOpc != ARM::t2RRX)
7798 unsigned NewOpc;
7801 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7802 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7803 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7804 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7808 TmpInst.setOpcode(NewOpc);
7843 unsigned newOpc;
7848 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7849 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7850 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7851 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7852 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7853 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7860 TmpInst.setOpcode(newOpc);
7913 unsigned NewOpc;
7916 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7917 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7918 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7919 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7920 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7921 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7924 TmpInst.setOpcode(NewOpc);
7953 unsigned NewOpc;
7956 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7957 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7958 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7959 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7962 TmpInst.setOpcode(NewOpc);
