Lines Matching refs:DestReg
115 unsigned DestReg, unsigned SrcReg,
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
170 unsigned DestReg, int FI,
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
204 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
205 MIB.addReg(DestReg, RegState::ImplicitDefine);
209 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
214 unsigned DestReg, unsigned BaseReg, int NumBytes,
217 if (NumBytes == 0 && DestReg != BaseReg) {
218 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
229 if (DestReg != ARM::SP && DestReg != BaseReg &&
235 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
241 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
242 .addReg(DestReg)
250 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
252 .addReg(DestReg, RegState::Kill)
256 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
257 .addReg(DestReg, RegState::Kill)
269 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
271 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
280 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
283 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
302 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
322 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
328 BaseReg = DestReg;
