Lines Matching refs:ISD
55 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
57 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
68 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
71 setOperationAction(ISD::ADD, VecTys[i], Legal);
72 setOperationAction(ISD::SUB, VecTys[i], Legal);
73 setOperationAction(ISD::LOAD, VecTys[i], Legal);
74 setOperationAction(ISD::STORE, VecTys[i], Legal);
75 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
78 setTargetDAGCombine(ISD::SHL);
79 setTargetDAGCombine(ISD::SRA);
80 setTargetDAGCombine(ISD::SRL);
81 setTargetDAGCombine(ISD::SETCC);
82 setTargetDAGCombine(ISD::VSELECT);
86 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
97 setTargetDAGCombine(ISD::AND);
98 setTargetDAGCombine(ISD::OR);
99 setTargetDAGCombine(ISD::SRA);
100 setTargetDAGCombine(ISD::VSELECT);
101 setTargetDAGCombine(ISD::XOR);
116 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
117 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
118 setOperationAction(ISD::MULHS, MVT::i32, Custom);
119 setOperationAction(ISD::MULHU, MVT::i32, Custom);
122 setOperationAction(ISD::MUL, MVT::i64, Legal);
124 setOperationAction(ISD::MUL, MVT::i64, Custom);
127 setOperationAction(ISD::MULHS, MVT::i64, Custom);
128 setOperationAction(ISD::MULHU, MVT::i64, Custom);
131 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
132 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
134 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
135 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
136 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
137 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
138 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::STORE, MVT::i32, Custom);
142 setTargetDAGCombine(ISD::ADDE);
143 setTargetDAGCombine(ISD::SUBE);
144 setTargetDAGCombine(ISD::MUL);
146 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
151 setOperationAction(ISD::LOAD, MVT::f64, Custom);
152 setOperationAction(ISD::STORE, MVT::f64, Custom);
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
159 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
160 setOperationAction(ISD::MUL, MVT::i32, Legal);
161 setOperationAction(ISD::MULHS, MVT::i32, Legal);
162 setOperationAction(ISD::MULHU, MVT::i32, Legal);
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
168 setOperationAction(ISD::SDIV, MVT::i32, Legal);
169 setOperationAction(ISD::UDIV, MVT::i32, Legal);
170 setOperationAction(ISD::SREM, MVT::i32, Legal);
171 setOperationAction(ISD::UREM, MVT::i32, Legal);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
176 setOperationAction(ISD::SELECT, MVT::i32, Legal);
177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
180 setOperationAction(ISD::SELECT, MVT::f32, Legal);
181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
185 setOperationAction(ISD::SELECT, MVT::f64, Legal);
186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
188 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
196 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
197 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
205 setOperationAction(ISD::MUL, MVT::i64, Legal);
206 setOperationAction(ISD::MULHS, MVT::i64, Legal);
207 setOperationAction(ISD::MULHU, MVT::i64, Legal);
211 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
212 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
213 setOperationAction(ISD::SDIV, MVT::i64, Legal);
214 setOperationAction(ISD::UDIV, MVT::i64, Legal);
215 setOperationAction(ISD::SREM, MVT::i64, Legal);
216 setOperationAction(ISD::UREM, MVT::i64, Legal);
220 setOperationAction(ISD::SETCC, MVT::i64, Legal);
221 setOperationAction(ISD::SELECT, MVT::i64, Legal);
222 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
247 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
250 setOperationAction(ISD::BITCAST, Ty, Legal);
251 setOperationAction(ISD::LOAD, Ty, Legal);
252 setOperationAction(ISD::STORE, Ty, Legal);
253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
254 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
255 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
257 setOperationAction(ISD::ADD, Ty, Legal);
258 setOperationAction(ISD::AND, Ty, Legal);
259 setOperationAction(ISD::CTLZ, Ty, Legal);
260 setOperationAction(ISD::CTPOP, Ty, Legal);
261 setOperationAction(ISD::MUL, Ty, Legal);
262 setOperationAction(ISD::OR, Ty, Legal);
263 setOperationAction(ISD::SDIV, Ty, Legal);
264 setOperationAction(ISD::SREM, Ty, Legal);
265 setOperationAction(ISD::SHL, Ty, Legal);
266 setOperationAction(ISD::SRA, Ty, Legal);
267 setOperationAction(ISD::SRL, Ty, Legal);
268 setOperationAction(ISD::SUB, Ty, Legal);
269 setOperationAction(ISD::UDIV, Ty, Legal);
270 setOperationAction(ISD::UREM, Ty, Legal);
271 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
272 setOperationAction(ISD::VSELECT, Ty, Legal);
273 setOperationAction(ISD::XOR, Ty, Legal);
276 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
277 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
278 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
279 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
282 setOperationAction(ISD::SETCC, Ty, Legal);
283 setCondCodeAction(ISD::SETNE, Ty, Expand);
284 setCondCodeAction(ISD::SETGE, Ty, Expand);
285 setCondCodeAction(ISD::SETGT, Ty, Expand);
286 setCondCodeAction(ISD::SETUGE, Ty, Expand);
287 setCondCodeAction(ISD::SETUGT, Ty, Expand);
296 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
299 setOperationAction(ISD::LOAD, Ty, Legal);
300 setOperationAction(ISD::STORE, Ty, Legal);
301 setOperationAction(ISD::BITCAST, Ty, Legal);
302 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
303 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
304 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
307 setOperationAction(ISD::FABS, Ty, Legal);
308 setOperationAction(ISD::FADD, Ty, Legal);
309 setOperationAction(ISD::FDIV, Ty, Legal);
310 setOperationAction(ISD::FEXP2, Ty, Legal);
311 setOperationAction(ISD::FLOG2, Ty, Legal);
312 setOperationAction(ISD::FMA, Ty, Legal);
313 setOperationAction(ISD::FMUL, Ty, Legal);
314 setOperationAction(ISD::FRINT, Ty, Legal);
315 setOperationAction(ISD::FSQRT, Ty, Legal);
316 setOperationAction(ISD::FSUB, Ty, Legal);
317 setOperationAction(ISD::VSELECT, Ty, Legal);
319 setOperationAction(ISD::SETCC, Ty, Legal);
320 setCondCodeAction(ISD::SETOGE, Ty, Expand);
321 setCondCodeAction(ISD::SETOGT, Ty, Expand);
322 setCondCodeAction(ISD::SETUGE, Ty, Expand);
323 setCondCodeAction(ISD::SETUGT, Ty, Expand);
324 setCondCodeAction(ISD::SETGE, Ty, Expand);
325 setCondCodeAction(ISD::SETGT, Ty, Expand);
359 case ISD::LOAD: return lowerLOAD(Op, DAG);
360 case ISD::STORE: return lowerSTORE(Op, DAG);
361 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
362 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
363 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
364 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
365 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
366 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
367 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
369 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
370 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
371 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
372 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
373 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
374 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
393 if (ADDCNode->getOpcode() != ISD::ADDC)
406 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
432 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
465 if (SUBCNode->getOpcode() != ISD::SUBC)
478 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
504 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
542 // the ISD::AND.
543 // - Removes redundant zero extensions performed by an ISD::AND.
591 // * N is a ISD::BUILD_VECTOR representing a constant splat
620 if (N->getOpcode() == ISD::BITCAST)
642 if (N->getOpcode() != ISD::XOR)
654 // Perform combines where ISD::OR is the root node.
674 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
774 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
808 return DAG.getNode(ISD::SHL, DL, VT, X,
821 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
828 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
885 // the ISD::SRA and ISD::SHL nodes.
886 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
904 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
949 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
953 case ISD::SETEQ:
954 case ISD::SETNE: return true;
955 case ISD::SETLT:
956 case ISD::SETLE:
957 case ISD::SETGT:
958 case ISD::SETGE: return IsV216;
959 case ISD::SETULT:
960 case ISD::SETULE:
961 case ISD::SETUGT:
962 case ISD::SETUGE: return !IsV216;
998 if (Op0->getOpcode() != ISD::SETCC)
1001 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
1004 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
1006 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1048 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
1050 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1055 if (NotOp->getOpcode() == ISD::OR)
1069 case ISD::ADDE:
1071 case ISD::AND:
1074 case ISD::OR:
1077 case ISD::SUBE:
1079 case ISD::MUL:
1081 case ISD::SHL:
1083 case ISD::SRA:
1085 case ISD::SRL:
1087 case ISD::VSELECT:
1089 case ISD::XOR:
1092 case ISD::SETCC:
1212 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1250 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1282 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1284 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1292 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1318 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1389 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1393 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1413 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1414 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1416 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1429 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1433 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1458 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1459 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1470 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1475 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1485 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1487 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1498 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1544 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1550 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1553 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1556 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1577 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1590 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1595 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1598 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1602 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1605 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1615 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1616 DAG.getNode(ISD::SHL, DL, VecTy, One,
1623 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1636 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1641 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1651 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1652 DAG.getNode(ISD::SHL, DL, VecTy, One,
1659 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1675 Op->getOperand(2), ISD::SETEQ);
1681 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1687 Op->getOperand(2), ISD::SETLE);
1693 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1699 Op->getOperand(2), ISD::SETULE);
1705 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1711 Op->getOperand(2), ISD::SETLT);
1717 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1723 Op->getOperand(2), ISD::SETULT);
1729 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1741 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1759 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1767 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1773 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1777 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1783 Op->getOperand(2), ISD::SETOEQ);
1787 Op->getOperand(2), ISD::SETOLE);
1791 Op->getOperand(2), ISD::SETOLT);
1795 Op->getOperand(2), ISD::SETONE);
1799 Op->getOperand(2), ISD::SETO);
1803 Op->getOperand(2), ISD::SETUEQ);
1807 Op->getOperand(2), ISD::SETULE);
1811 Op->getOperand(2), ISD::SETULT);
1815 Op->getOperand(2), ISD::SETUO);
1819 Op->getOperand(2), ISD::SETUNE);
1822 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1826 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1830 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1844 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
1850 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1851 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1855 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1858 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1862 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1867 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1868 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1873 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1876 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1879 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1883 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1887 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1917 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1934 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1935 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1943 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1944 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1999 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2005 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2011 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2018 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2019 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2026 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2028 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2033 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2039 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2042 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2060 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2070 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2076 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2100 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2106 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2112 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2118 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2124 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2130 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2139 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2142 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2155 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2223 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2261 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2263 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2265 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2289 if (Op->getOpcode() == ISD::UNDEF)
2305 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2369 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2385 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2669 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);
