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Lines Matching refs:isZExt

144                     bool isZExt, unsigned DestReg);
146 const TargetRegisterClass *RC, bool IsZExt = true,
153 unsigned DestReg, bool IsZExt);
429 bool IsZExt, unsigned FP64LoadOpc) {
457 Opc = (IsZExt ?
462 Opc = (IsZExt ?
734 bool IsZExt, unsigned DestReg) {
757 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
758 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
780 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
782 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
786 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
788 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
805 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
811 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
1265 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1277 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1625 unsigned DestReg, bool IsZExt) {
1632 if (!IsZExt) {
1727 bool IsZExt = isa<ZExtInst>(I);
1753 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
2106 bool IsZExt = false;
2113 IsZExt = true;
2124 IsZExt = true;
2161 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))