Lines Matching refs:v4i32
415 // We promote all non-typed operations to v4i32.
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2142 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2278 case MVT::v4i32:
2631 case MVT::v4i32:
2792 case MVT::v4i32:
2826 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2970 case MVT::v4i32:
4256 case MVT::v4i32:
4400 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4633 case MVT::v4i32:
4703 v4i32 ||
5435 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5527 // Canonicalize all zero vectors to be v4i32.
5528 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5530 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5558 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5572 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5579 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6017 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6018 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6052 if (Op.getValueType() == MVT::v4i32) {
6055 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6056 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6069 LHS, RHS, DAG, dl, MVT::v4i32);
6072 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6076 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
8116 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8193 if (BaseLoad.getValueType() != MVT::v4i32)
8194 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8196 if (ExtraLoad.getValueType() != MVT::v4i32)
8197 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8212 if (VT != MVT::v4i32)
