Lines Matching refs:DstReg
125 unsigned DstReg;
128 DstReg = MI.getOperand(Chan).getReg();
130 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
133 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
154 unsigned DstReg;
157 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
159 DstReg = MI.getOperand(Chan-2).getReg();
162 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
182 unsigned DstReg = MI.getOperand(0).getReg();
186 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
201 unsigned DstReg = MI.getOperand(0).getReg();
202 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
205 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
271 unsigned DstReg = MI.getOperand(
301 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
305 Mask = (Chan != TRI.getHWRegChan(DstReg));
306 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
307 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
327 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
