Lines Matching defs:DAG
1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
11 /// \brief Custom DAG lowering for R600
564 // Custom DAG Lowering Operations
567 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
568 MachineFunction &MF = DAG.getMachineFunction();
571 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
572 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
573 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
574 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
576 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
578 case ISD::FSIN: return LowerTrig(Op, DAG);
579 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
580 case ISD::STORE: return LowerSTORE(Op, DAG);
582 SDValue Result = LowerLOAD(Op, DAG);
589 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
590 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
600 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
608 DAG.getConstant(0, MVT::i32), // SWZ_X
609 DAG.getConstant(1, MVT::i32), // SWZ_Y
610 DAG.getConstant(2, MVT::i32), // SWZ_Z
611 DAG.getConstant(3, MVT::i32) // SWZ_W
613 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
628 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
632 MachineFunction &MF = DAG.getMachineFunction();
635 return DAG.getCopyFromReg(DAG.getEntryNode(),
636 SDLoc(DAG.getEntryNode()), Reg, VT);
644 const MachineFunction &MF = DAG.getMachineFunction();
647 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
648 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
649 return DAG.getTargetExtractSubreg(
653 MachineFunction &MF = DAG.getMachineFunction();
659 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
660 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
661 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
662 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
665 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
666 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
669 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
670 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
682 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
683 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
686 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
687 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
689 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
743 DAG.getConstant(TextureOp, MVT::i32),
745 DAG.getConstant(0, MVT::i32),
746 DAG.getConstant(1, MVT::i32),
747 DAG.getConstant(2, MVT::i32),
748 DAG.getConstant(3, MVT::i32),
752 DAG.getConstant(0, MVT::i32),
753 DAG.getConstant(1, MVT::i32),
754 DAG.getConstant(2, MVT::i32),
755 DAG.getConstant(3, MVT::i32),
763 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
767 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
768 DAG.getConstant(0, MVT::i32)),
769 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
770 DAG.getConstant(0, MVT::i32)),
771 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
772 DAG.getConstant(1, MVT::i32)),
773 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
774 DAG.getConstant(1, MVT::i32)),
775 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
776 DAG.getConstant(2, MVT::i32)),
777 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
778 DAG.getConstant(2, MVT::i32)),
779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
780 DAG.getConstant(3, MVT::i32)),
781 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
782 DAG.getConstant(3, MVT::i32))
784 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
788 return LowerImplicitParameter(DAG, VT, DL, 0);
790 return LowerImplicitParameter(DAG, VT, DL, 1);
792 return LowerImplicitParameter(DAG, VT, DL, 2);
794 return LowerImplicitParameter(DAG, VT, DL, 3);
796 return LowerImplicitParameter(DAG, VT, DL, 4);
798 return LowerImplicitParameter(DAG, VT, DL, 5);
800 return LowerImplicitParameter(DAG, VT, DL, 6);
802 return LowerImplicitParameter(DAG, VT, DL, 7);
804 return LowerImplicitParameter(DAG, VT, DL, 8);
807 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
810 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
813 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
816 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
819 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
822 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
826 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
837 SelectionDAG &DAG) const {
840 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
842 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
848 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
857 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
866 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
875 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
882 SDValue RES = LowerSDIVREM(Op, DAG);
891 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
893 SDValue one = DAG.getConstant(1, HalfVT);
894 SDValue zero = DAG.getConstant(0, HalfVT);
898 DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
899 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
902 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
903 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
906 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
907 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
910 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
912 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
918 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
922 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
924 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
925 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
928 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
929 DAG.getConstant(halfBitWidth - 1, HalfVT));
930 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
931 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
933 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
934 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
937 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
939 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
940 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
942 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
946 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
948 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
949 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
950 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
953 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
954 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
962 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
972 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
973 Vector, DAG.getConstant(i, getVectorIdxTy())));
976 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
980 SelectionDAG &DAG) const {
990 Vector = vectorToVerticalVector(DAG, Vector);
991 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
996 SelectionDAG &DAG) const {
1006 Vector = vectorToVerticalVector(DAG, Vector);
1007 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
1009 return vectorToVerticalVector(DAG, Insert);
1012 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1017 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1018 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
1019 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1020 DAG.getConstantFP(0.15915494309, MVT::f32)),
1021 DAG.getConstantFP(0.5, MVT::f32)));
1033 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
1034 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
1035 DAG.getConstantFP(-0.5, MVT::f32)));
1039 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
1040 DAG.getConstantFP(3.14159265359, MVT::f32));
1043 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
1050 SDValue Zero = DAG.getConstant(0, VT);
1051 SDValue One = DAG.getConstant(1, VT);
1053 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1054 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1055 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1056 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1063 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1064 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1066 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
1067 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
1068 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
1070 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
1073 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1074 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1076 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1079 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1086 SDValue Zero = DAG.getConstant(0, VT);
1087 SDValue One = DAG.getConstant(1, VT);
1091 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1092 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1093 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1094 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1101 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
1102 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1104 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1105 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1106 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1108 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1109 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1111 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1112 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1114 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1117 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1118 return DAG.getNode(
1122 Op, DAG.getConstantFP(0.0f, MVT::f32),
1123 DAG.getCondCode(ISD::SETNE)
1127 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
1131 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1137 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1138 DAG.getConstant(ByteOffset, MVT::i32), // PTR
1153 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1185 CC = DAG.getCondCode(InverseCC);
1191 CC = DAG.getCondCode(SwapInvCC);
1199 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1219 CC = DAG.getCondCode(CCSwapped);
1227 CC = DAG.getCondCode(CCSwapped);
1240 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1241 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1256 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1259 DAG.getCondCode(CCOpcode));
1260 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1268 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
1269 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
1271 HWTrue = DAG.getConstant(-1, CompareVT);
1272 HWFalse = DAG.getConstant(0, CompareVT);
1280 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1282 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1285 DAG.getCondCode(ISD::SETNE));
1295 SelectionDAG &DAG) const {
1310 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1311 DAG.getConstant(SRLPad, MVT::i32));
1343 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1350 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1362 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1365 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1367 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1368 DAG.getConstant(2, MVT::i32));
1369 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1370 DAG.getConstant(0x00000003, VT));
1371 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1372 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1373 DAG.getConstant(3, VT));
1374 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1375 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1380 DAG.getConstant(0, MVT::i32),
1381 DAG.getConstant(0, MVT::i32),
1384 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1386 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1392 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1393 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1394 Ptr, DAG.getConstant(2, MVT::i32)));
1399 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1411 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1417 const MachineFunction &MF = DAG.getMachineFunction();
1422 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1435 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1436 DAG.getConstant(PtrIncr, MVT::i32));
1437 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1438 Value, DAG.getConstant(i, MVT::i32));
1440 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1442 DAG.getTargetConstant(Channel, MVT::i32));
1444 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1447 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1449 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1450 DAG.getTargetConstant(0, MVT::i32)); // Channel
1497 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1506 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1512 return DAG.getMergeValues(Ops, DL);
1518 SplitVectorLoad(Op, DAG),
1521 return DAG.getMergeValues(MergedValues, DL);
1539 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1540 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1541 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1549 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1553 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1554 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1555 DAG.getConstant(LoadNode->getAddressSpace() -
1561 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1562 DAG.getConstant(0, MVT::i32));
1569 return DAG.getMergeValues(MergedValues, DL);
1573 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1583 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1584 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1589 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1590 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1593 return DAG.getMergeValues(MergedValues, DL);
1601 const MachineFunction &MF = DAG.getMachineFunction();
1606 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1619 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1620 DAG.getConstant(PtrIncr, MVT::i32));
1621 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1623 DAG.getTargetConstant(Channel, MVT::i32),
1627 Loads[i] = DAG.getUNDEF(ElemVT);
1629 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1630 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1632 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1634 DAG.getTargetConstant(0, MVT::i32), // Channel
1643 return DAG.getMergeValues(Ops, DL);
1646 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1651 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1663 SDLoc DL, SelectionDAG &DAG,
1666 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1667 getTargetMachine(), ArgLocs, *DAG.getContext());
1668 MachineFunction &MF = DAG.getMachineFunction();
1673 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1684 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1689 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1704 SDValue Arg = DAG.getExtLoad(Ext, DL, VT, Chain,
1705 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1722 SelectionDAG &DAG, SDValue VectorEntry,
1742 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1745 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1753 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1760 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1764 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1798 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1804 SDValue Swz[4], SelectionDAG &DAG) const {
1809 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1813 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1817 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1821 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1829 // Custom DAG Optimizations
1834 SelectionDAG &DAG = DCI.DAG;
1842 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1867 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1870 DAG.getConstant(-1, MVT::i32), // True
1871 DAG.getConstant(0, MVT::i32), // Flase
1909 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1921 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1922 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1927 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1944 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1986 return DAG.getSelectCC(SDLoc(N),
2014 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
2015 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
2043 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
2044 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
2054 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2056 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
2064 Neg = DAG.getTargetConstant(1, MVT::i32);
2070 Abs = DAG.getTargetConstant(1, MVT::i32);
2123 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2166 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
2168 Src = DAG.getRegister(ImmReg, MVT::i32);
2179 SelectionDAG &DAG) const {
2181 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
2233 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2234 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2239 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2240 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2255 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
2256 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
2292 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2293 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
