Lines Matching refs:SELECT_CC
79 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
80 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
153 setTargetDAGCombine(ISD::SELECT_CC);
579 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1173 // select_cc f32, f32, -1, 0, cc_supported
1174 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
1175 // select_cc i32, i32, -1, 0, cc_supported
1199 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1206 // select_cc f32, 0.0, f32, f32, cc_supported
1207 // select_cc f32, 0.0, i32, i32, cc_supported
1208 // select_cc i32, 0, f32, f32, cc_supported
1209 // select_cc i32, 0, i32, i32, cc_supported
1256 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1264 // this SELECT_CC, so we must lower it.
1278 // Lower this unsupported SELECT_CC into a combination of two supported
1279 // SELECT_CC operations.
1280 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1282 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1848 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1849 // (i32 select_cc f32, f32, -1, 0 cc)
1859 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1867 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1950 case ISD::SELECT_CC: {
1962 if (LHS.getOpcode() != ISD::SELECT_CC) {
