Lines Matching refs:v2f32
39 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
689 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
