Lines Matching refs:v4i32
37 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
66 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
118 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
132 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
137 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1384 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1543 EVT NewVT = MVT::v4i32;
1553 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
