Lines Matching refs:TII
61 const R600InstrInfo *TII;
76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
88 if (TII->isPredicated(BI))
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
98 if (isTrans || TII->isTransOnly(BI)) {
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
154 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
155 TRI(TII->getRegisterInfo()) {
173 if (TII->isVector(*MI))
175 if (!TII->isALUInstr(MI->getOpcode()))
181 if (TII->isLDSInstr(MI->getOpcode()))
193 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
194 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
213 bool ARDef = TII->definesAddressRegister(MII) ||
214 TII->definesAddressRegister(MIJ);
215 bool ARUse = TII->usesAddressRegister(MII) ||
216 TII->usesAddressRegister(MIJ);
230 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
238 isTransSlot = TII->isTransOnly(MI);
245 !TII->isVectorOnly(MI) && VLIW5) {
256 if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
272 if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
289 if (isTransSlot && TII->readsLDSSrcReg(MI))
307 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
311 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
324 if (TII->isTransOnly(MI))
331 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
379 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
