Lines Matching defs:RegClass
1180 /// \brief Test if RegClass is one of the VSrc classes
1181 static bool isVSrc(unsigned RegClass) {
1182 return AMDGPU::VSrc_32RegClassID == RegClass ||
1183 AMDGPU::VSrc_64RegClassID == RegClass;
1186 /// \brief Test if RegClass is one of the SSrc classes
1187 static bool isSSrc(unsigned RegClass) {
1188 return AMDGPU::SSrc_32RegClassID == RegClass ||
1189 AMDGPU::SSrc_64RegClassID == RegClass;
1283 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1315 /// \brief Does "Op" fit into register class "RegClass" ?
1317 unsigned RegClass) const {
1323 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1328 unsigned RegClass,
1332 if (RegClass == AMDGPU::VSrc_32RegClassID)
1333 RegClass = AMDGPU::VReg_32RegClassID;
1334 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1335 RegClass = AMDGPU::VReg_64RegClassID;
1340 if (fitsRegClass(DAG, Operand, RegClass))
1351 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1402 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1403 if (isVSrc(RegClass))
1405 else if (isSSrc(RegClass))
1439 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1440 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1444 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1449 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1451 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1456 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1473 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1479 (!fitsRegClass(DAG, Ops[i], RegClass) &&
