Lines Matching refs:v8f32
50 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);73 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);179 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
