Lines Matching refs:SIInstrInfo
1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
16 #include "SIInstrInfo.h"
27 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
36 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
171 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
185 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
199 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
239 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
250 Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
296 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
310 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
368 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
410 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
418 bool SIInstrInfo::isMov(unsigned Opcode) const {
430 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
435 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
449 // an SIInstrInfo function that reutrns bool rather than int.
454 bool SIInstrInfo::isDS(uint16_t Opcode) const {
458 int SIInstrInfo::isMIMG(uint16_t Opcode) const {
462 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
466 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
470 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
474 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
478 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
482 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
486 bool SIInstrInfo
511 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
523 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
544 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
678 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
730 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
734 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
746 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
758 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
778 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
804 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
826 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
856 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1107 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1173 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1356 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1362 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1366 void SIInstrInfo::splitScalar64BitUnaryOp(
1418 void SIInstrInfo::splitScalar64BitBinaryOp(
1482 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1522 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1540 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1558 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1576 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
