Lines Matching refs:Op0
44 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
47 SDValue Op0, Op1;
49 // The opcode that should be used to compare Op0 and Op1.
1137 if (!C.Op0.hasOneUse() ||
1138 C.Op0.getOpcode() != ISD::LOAD ||
1143 auto *Load = cast<LoadSDNode>(C.Op0);
1154 // Make sure that ConstOp1 is in range of C.Op0.
1188 if (C.Op0.getValueType() != MVT::i32 ||
1190 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1228 if (C.Op0.getValueType() == MVT::f128)
1250 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1269 unsigned Opcode0 = C.Op0.getOpcode();
1276 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1277 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1298 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1301 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1302 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1303 C.Op0 = SDValue(N, 0);
1318 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1321 C.Op0 = SDValue(N, 0);
1337 if (C.Op0.getOpcode() == ISD::SHL &&
1338 C.Op0.getValueType() == MVT::i64 &&
1341 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1343 SDValue ShlOp0 = C.Op0.getOperand(0);
1349 C.Op0 = SDValue(N, 0);
1361 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1362 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1365 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1367 <= C.Op0.getValueType().getSizeInBits()) {
1371 C.Op0 = C.Op0.getOperand(0);
1372 C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
1502 if (C.Op0.getOpcode() == ISD::AND) {
1503 NewC.Op0 = C.Op0.getOperand(0);
1504 NewC.Op1 = C.Op0.getOperand(1);
1513 if (NewC.Op0.getValueType() != MVT::i64 ||
1526 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1534 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1537 NewC.Op0.getOpcode() == ISD::SHL &&
1538 isSimpleShift(NewC.Op0, ShiftVal) &&
1543 NewC.Op0 = NewC.Op0.getOperand(0);
1546 NewC.Op0.getOpcode() == ISD::SRL &&
1547 isSimpleShift(NewC.Op0, ShiftVal) &&
1552 NewC.Op0 = NewC.Op0.getOperand(0);
1563 C.Op0 = NewC.Op0;
1567 C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
1577 if (C.Op0.getValueType().isFloatingPoint()) {
1591 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
1606 std::swap(C.Op0, C.Op1);
1617 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
1622 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
1625 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
1632 unsigned Extend, SDValue Op0, SDValue Op1,
1634 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1636 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1643 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1644 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1645 // on the extended Op0 and (unextended) Op1. Store the even register result
1649 SDValue Op0, SDValue Op1,
1651 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1752 if (isAbsolute(C.Op0, TrueOp, FalseOp))
1754 if (isAbsolute(C.Op0, FalseOp, TrueOp))
2090 SDValue Op0 = Op.getOperand(0);
2098 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2111 Op0, Op1, Ops[1], Ops[0]);
