Lines Matching refs:ISD
313 if (N.getOpcode() != ISD::LOAD)
325 case ISD::ADD:
326 case ISD::ADDC:
327 case ISD::ADDE:
328 case ISD::AND:
329 case ISD::OR:
330 case ISD::XOR: {
359 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
378 assert(Chain.getOpcode() == ISD::TokenFactor &&
386 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
419 LD->getAddressingMode() != ISD::UNINDEXED ||
420 LD->getExtensionType() != ISD::NON_EXTLOAD)
424 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
439 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
500 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
521 if (N->getOpcode() == ISD::FP_EXTEND)
532 if (N->getOpcode() == ISD::FP_ROUND)
545 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
785 if (Shift.getOpcode() != ISD::SRL ||
799 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
800 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
802 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
828 if (Shift.getOpcode() != ISD::SHL ||
846 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
847 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
895 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
925 if (X.getOpcode() == ISD::ANY_EXTEND) {
946 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
952 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
954 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
1000 case ISD::Constant: {
1013 case ISD::LOAD:
1018 case ISD::FrameIndex:
1028 case ISD::SHL:
1061 case ISD::SRL: {
1066 if (And.getOpcode() != ISD::AND) break;
1088 case ISD::SMUL_LOHI:
1089 case ISD::UMUL_LOHI:
1093 case ISD::MUL:
1111 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1129 case ISD::SUB: {
1159 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1160 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1161 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1162 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1186 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1196 case ISD::ADD: {
1229 case ISD::OR:
1243 case ISD::AND: {
1251 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1318 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1319 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1360 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1362 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1377 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1379 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1411 if (N->getOpcode() != ISD::TargetConstantPool &&
1412 N->getOpcode() != ISD::TargetJumpTable &&
1413 N->getOpcode() != ISD::TargetGlobalAddress &&
1414 N->getOpcode() != ISD::TargetExternalSymbol &&
1415 N->getOpcode() != ISD::TargetBlockAddress)
1526 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1551 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1745 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1752 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1753 Val.getOperand(0).getOpcode() == ISD::SUB &&
1786 case ISD::ATOMIC_LOAD_OR:
1789 case ISD::ATOMIC_LOAD_AND:
1792 case ISD::ATOMIC_LOAD_XOR:
1795 case ISD::ATOMIC_LOAD_ADD:
1802 ISD::TargetConstant);
1868 if (UI->getOpcode() != ISD::CopyToReg)
1940 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1945 if (!ISD::isNormalLoad(Load.getNode())) return false;
1972 } else if (Chain.getOpcode() == ISD::TokenFactor) {
2000 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2074 case ISD::INTRINSIC_W_CHAIN: {
2129 case ISD::ATOMIC_LOAD_XOR:
2130 case ISD::ATOMIC_LOAD_AND:
2131 case ISD::ATOMIC_LOAD_OR:
2132 case ISD::ATOMIC_LOAD_ADD: {
2138 case ISD::AND:
2139 case ISD::OR:
2140 case ISD::XOR: {
2146 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2164 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2191 case ISD::AND: Op = X86::AND32ri8; break;
2192 case ISD::OR: Op = X86::OR32ri8; break;
2193 case ISD::XOR: Op = X86::XOR32ri8; break;
2202 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2203 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2204 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2241 case ISD::SMUL_LOHI:
2242 case ISD::UMUL_LOHI: {
2246 bool isSigned = Opcode == ISD::SMUL_LOHI;
2389 case ISD::SDIVREM:
2390 case ISD::UDIVREM: {
2394 bool isSigned = Opcode == ISD::SDIVREM;
2568 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2572 if ((N0.getNode()->getOpcode() == ISD::AND ||
2697 case ISD::STORE: {
