Lines Matching full:pshuflw
3367 case X86ISD::PSHUFLW:
3407 case X86ISD::PSHUFLW:
3730 /// is suitable for input to PSHUFLW.
4632 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
5152 case X86ISD::PSHUFLW:
7398 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7420 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8143 // 1. [all] pshuflw, pshufhw, optional move
8146 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8244 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8254 pshuflw = false;
8262 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8264 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8265 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8305 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8324 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9483 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
13815 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16598 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18437 case X86ISD::PSHUFLW:
18478 case X86ISD::PSHUFLW:
18505 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18515 case X86ISD::PSHUFLW:
18563 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
18572 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
18589 case X86ISD::PSHUFLW:
18602 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
18613 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18655 case X86ISD::PSHUFLW:
18673 case X86ISD::PSHUFLW:
18686 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
18701 (V.getOpcode() == X86ISD::PSHUFLW ||
18711 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
18712 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22018 case X86ISD::PSHUFLW:
