Lines Matching refs:ANY_EXTEND
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
1218 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1575 setTargetDAGCombine(ISD::ANY_EXTEND);
1898 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2708 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
9934 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10040 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10070 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11192 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11994 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12001 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12006 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15723 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16199 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19757 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
19762 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20258 ((N00.getOpcode() == ISD::ANY_EXTEND ||
20375 case ISD::ANY_EXTEND:
20477 assert((N->getOpcode() == ISD::ANY_EXTEND ||
20532 case ISD::ANY_EXTEND:
21516 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22000 case ISD::ANY_EXTEND:
22051 case ISD::ANY_EXTEND:
22095 case ISD::ANY_EXTEND:
