Lines Matching refs:BUILD_VECTOR
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
934 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
984 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
993 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
998 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
999 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1298 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1417 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1582 setTargetDAGCombine(ISD::BUILD_VECTOR);
4811 if (N->getOpcode() != ISD::BUILD_VECTOR)
4874 if (Opc != ISD::BUILD_VECTOR ||
4881 if (Opc != ISD::BUILD_VECTOR ||
4901 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4904 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4910 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4916 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4922 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4927 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4947 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4949 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4953 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5250 if (V.getOpcode() == ISD::BUILD_VECTOR)
5398 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5446 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5478 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5642 /// load which has the same value as a build_vector whose operands are 'elts'.
5744 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5768 case ISD::BUILD_VECTOR: {
5783 // BUILD_VECTOR node.
5799 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5991 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6003 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6009 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6057 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6075 /// This function checks that the build_vector \p N in input implements a
6231 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6242 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6321 // Don't try to fold this build_vector into a VSELECT if it has
6345 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6373 // Count the number of UNDEF operands in the build_vector in input.
6382 // Early exit if this is either a build_vector of all UNDEFs or all the
6449 // Fold this build_vector into a single horizontal add/sub.
6454 // Do not try to expand this build_vector into a pair of horizontal
6459 // Convert this build_vector into a pair of horizontal binop followed by
6482 // Don't try to expand this build_vector into a pair of horizontal add/sub
6487 // Convert this build_vector into two horizontal add/sub followed by
6696 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6698 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
8139 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8440 DAG.getNode(ISD::BUILD_VECTOR, dl,
8458 DAG.getNode(ISD::BUILD_VECTOR, dl,
8701 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8732 // Construct the output using a BUILD_VECTOR.
8733 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
8904 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
8906 // BUILD_VECTOR (load), undef
9545 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9597 // This function assumes its argument is a BUILD_VECTOR of constants or
11262 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12159 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12324 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13435 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13467 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15246 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15259 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15272 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15292 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15305 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15318 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15332 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15393 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15415 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15494 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15558 // Do this only if the vector shift count is a constant build_vector.
15585 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15602 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
15740 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15749 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
15750 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16025 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16177 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16336 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16471 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18344 // V UNDEF BUILD_VECTOR UNDEF
18351 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18867 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19645 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
19726 // build_vector of constants. This will be taken care in a later
19757 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
19762 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20523 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22029 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
