Lines Matching refs:SETCC
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
550 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
858 setOperationAction(ISD::SETCC, VT, Expand);
973 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
974 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
975 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
976 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
1198 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1200 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1201 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1339 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1408 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1409 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1580 setTargetDAGCombine(ISD::SETCC);
11637 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11700 // Truncate operations may prevent the merge of the SETCC instruction
11734 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11740 UI->getOpcode() != ISD::SETCC &&
11846 // from the setcc node.
12010 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12034 default: llvm_unreachable("Unexpected SETCC condition");
12067 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12110 default: llvm_unreachable("Unexpected SETCC condition");
12217 // In AVX-512 architecture setcc returns mask with i1 elements,
12225 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12236 default: llvm_unreachable("Unexpected SETCC condition");
12406 && "SetCC type must be 8-bit or 1-bit integer");
12432 // If the input is a setcc, then reuse the input setcc or use a new one with
12434 if (Op0.getOpcode() == X86ISD::SETCC) {
12442 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12446 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12447 return SetCC;
12465 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12468 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12469 return SetCC;
12520 if (Cond.getOpcode() == ISD::SETCC &&
12542 if (Cond.getOpcode() == ISD::SETCC) {
12552 if (Cond.getOpcode() == X86ISD::SETCC &&
12607 // setting operand in place of the X86ISD::SETCC.
12609 if (CondOpcode == X86ISD::SETCC ||
12807 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
12813 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12815 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
12819 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
12820 // 1 and that the SETCC node has a single use.
12826 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12841 if (Cond.getOpcode() == ISD::SETCC) {
12842 // Check for setcc([su]{add,sub,mul}o == 0).
12879 // setting operand in place of the X86ISD::SETCC.
12881 if (CondOpcode == X86ISD::SETCC ||
13009 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13018 } else if (Cond.getOpcode() == ISD::SETCC &&
13049 } else if (Cond.getOpcode() == ISD::SETCC &&
13579 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13581 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13857 // or testp pattern and a setcc for the result.
13917 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
13918 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13927 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
13928 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14083 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14086 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14559 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14562 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15770 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
15771 // looks for this combo and may remove the "setcc" instruction if the "setcc"
15822 SDValue SetCC =
15823 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15827 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15835 SDValue SetCC =
15836 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
15840 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15987 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16207 case ISD::SETCC: return LowerSETCC(Op, DAG);
16416 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16505 case X86ISD::SETCC: return "X86ISD::SETCC";
18234 case X86ISD::SETCC:
19226 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19394 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
19416 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
19490 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
19511 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19571 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
19597 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19598 // Check if SETCC has already been promoted
19777 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
19781 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
19782 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
19785 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
19786 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
19802 // an SetCC or extended from it.
19806 SDValue SetCC;
19812 SetCC = Op2;
19814 SetCC = Op1;
19827 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
19828 SetCC.getOpcode() == ISD::TRUNCATE ||
19829 SetCC.getOpcode() == ISD::AND) {
19830 if (SetCC.getOpcode() == ISD::AND) {
19833 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
19836 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
19841 SetCC = SetCC.getOperand(OpIdx);
19844 SetCC = SetCC.getOperand(0);
19847 switch (SetCC.getOpcode()) {
19855 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
19858 case X86ISD::SETCC:
19860 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
19863 return SetCC.getOperand(1);
19866 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
19867 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
19873 SDValue Op = SetCC.getOperand(0);
19898 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
19901 return SetCC.getOperand(3);
19958 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
19962 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19976 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
19979 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20017 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20335 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21600 // ISD::SETCC is always legalized to i8.
21740 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
21777 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
21874 SDValue SetCC = Ext.getOperand(0);
21875 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
21878 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
21882 SDValue Cmp = SetCC.getOperand(1);
22006 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22007 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
