Lines Matching refs:SIGN_EXTEND
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
1212 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1395 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1398 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1576 setTargetDAGCombine(ISD::SIGN_EXTEND);
1894 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2696 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
11207 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11904 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
15721 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16198 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19035 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
19172 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19377 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
19762 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20373 case ISD::SIGN_EXTEND:
20479 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
20541 case ISD::SIGN_EXTEND:
21517 N0.getOpcode() == ISD::SIGN_EXTEND)) {
21529 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
21668 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
21673 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
21815 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22002 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22049 case ISD::SIGN_EXTEND:
22093 case ISD::SIGN_EXTEND:
