Lines Matching refs:v16i16
1138 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1189 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1192 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1195 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1237 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1242 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1247 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1252 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1253 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1255 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1260 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1265 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1270 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1307 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1392 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
3703 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3715 if (VT == MVT::v16i16) {
3732 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3744 if (VT == MVT::v16i16) {
4612 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4636 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
6425 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6469 VT == MVT::v16i16) && Subtarget->hasAVX()) {
8025 if (!hasInt256 && VT == MVT::v16i16)
8034 // Blend for v16i16 should be symetric for the both lanes.
8382 /// \brief v16i16 shuffles
8584 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9219 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9567 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9608 // Blend for v16i16 should be symetric for the both lanes.
9651 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9690 case MVT::v16i16:
11092 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12767 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15220 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15284 MVT::v16i16, R, ShiftAmt,
15297 MVT::v16i16, R, ShiftAmt,
15388 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15456 case MVT::v16i16:
15467 case MVT::v16i16:
15480 case MVT::v16i16:
15561 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
15719 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
15858 case MVT::v16i16:
19100 case MVT::v16i16:
19187 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19514 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
19724 // We explicitly check against v8i16 and v16i16 because, although
19728 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20296 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21911 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21944 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22639 case MVT::v16i16:
