Lines Matching refs:v16i32
1329 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1347 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1376 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1377 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1380 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1381 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1393 v16i32, Custom);
1395 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1404 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1424 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1427 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1429 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1432 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1435 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1438 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1443 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1444 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1445 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1449 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
4922 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
6514 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
9512 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9777 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9975 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11128 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11206 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12740 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15081 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15222 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15389 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15457 case MVT::v16i32:
15468 case MVT::v16i32:
15481 case MVT::v16i32:
15540 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
22647 case MVT::v16i32:
