Lines Matching refs:v16i8
945 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
950 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
960 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
974 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
978 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1010 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1011 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1091 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1097 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1117 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1120 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1123 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1221 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1388 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1397 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1805 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
5398 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5443 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
7667 /// \brief Generic lowering of v16i8 shuffles.
7669 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7678 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7679 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7680 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7758 ISD::BITCAST, DL, MVT::v16i8,
7765 MVT::v16i8, V1, V1);
7774 ISD::BITCAST, DL, MVT::v16i8,
7800 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7801 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7803 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
7831 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
7857 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
7859 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
7873 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
7894 case MVT::v16i8:
8301 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8401 // v16i8 shuffles - Prefer shuffles in the following order:
8439 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8441 MVT::v16i8, pshufbMask));
8457 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8459 MVT::v16i8, pshufbMask));
8460 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8529 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8562 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8583 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9219 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9573 if (VT == MVT::v16i8) {
9854 // TODO: handle v16i8.
9926 else if (VT == MVT::v16i8)
11092 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11280 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11281 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11287 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11288 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11289 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12767 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15234 if (VT == MVT::v16i8) {
15672 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
15716 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18500 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19107 case MVT::v16i8:
19116 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19369 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
19371 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
19513 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20694 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22630 case MVT::v16i8:
