Lines Matching refs:v2i64
948 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
953 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
955 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
963 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
973 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
985 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
999 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1010 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1011 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1019 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1021 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1023 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1025 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1027 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1032 // Custom lower v2i64 and v2f64 selects.
1034 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1036 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1085 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1110 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1127 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1130 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1805 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1938 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2705 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2706 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3695 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5557 EVT ShVT = MVT::v2i64;
5716 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5717 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6576 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6993 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
6994 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6995 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7009 ISD::BITCAST, DL, MVT::v2i64,
7020 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7660 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7661 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7664 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7884 case MVT::v2i64:
8225 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8226 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8227 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8577 case MVT::v2i64:
8581 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8626 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8930 assert(VT != MVT::v2i64 && "unsupported shuffle type");
8994 // movl and movlp will both match v2i64, but v2i64 is never matched by
9322 (VT == MVT::v2f64 || VT == MVT::v2i64))
9329 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9367 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9473 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10796 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
10848 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
10849 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10852 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11087 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11088 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11234 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11236 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11269 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11395 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11606 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12307 if (VT == MVT::v2i64) {
12779 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15049 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15051 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15062 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15063 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15080 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15142 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15166 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15218 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15229 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15330 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15384 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15451 case MVT::v2i64:
15475 case MVT::v2i64:
15491 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15545 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15549 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15663 CastVT = MVT::v2i64;
16332 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16337 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16338 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19647 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
19678 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
19679 // (v2i64 (bitcast B)))))
19686 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
19687 // (v2i64 (bitcast A)))))
19707 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20294 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
20591 if (VT != MVT::v2i64 && VT != MVT::v4i64)
20628 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22633 case MVT::v2i64:
