Lines Matching refs:v4i32
947 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
952 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
954 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
956 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
957 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
962 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
976 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1010 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1086 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1099 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1128 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1131 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1133 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1223 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1379 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1383 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1704 return MVT::v4i32;
1805 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
3693 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3992 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4901 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4949 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4953 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5478 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5499 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
6394 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6514 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6521 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6524 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6577 EVT VecVT = MVT::v4i32;
6623 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
7003 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7004 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7010 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7127 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7128 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7129 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7137 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7145 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7216 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7217 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7405 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7406 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7888 case MVT::v4i32:
8563 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8581 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8582 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8583 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8626 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8935 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
8948 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
8954 // v4i32 or v4f32
9008 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9048 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9334 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9370 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9722 MVT::v4i32,
9748 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
9862 MVT::v4i32, Vec),
10073 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10798 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
10801 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
10802 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
10816 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
10817 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
10837 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11082 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11083 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11086 // v4i32 -> v4i64
11087 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11088 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11094 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11223 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11224 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11238 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11239 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11274 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11277 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11291 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11292 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11296 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12312 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12313 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12320 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12324 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12327 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12328 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12331 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12332 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12337 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12338 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12339 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12341 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12342 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12345 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12356 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12357 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12360 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12364 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12365 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12368 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12765 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
12775 // v4i32 to v4i64
12778 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
12779 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13467 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15038 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15039 if (VT == MVT::v4i32) {
15080 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15156 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15166 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15218 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15385 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15452 case MVT::v4i32:
15464 case MVT::v4i32:
15476 case MVT::v4i32:
15545 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15549 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15552 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
15560 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
15590 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
15602 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
15605 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
15611 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
15618 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
15623 if (VT == MVT::v4i32) {
15655 EVT CastVT = MVT::v4i32;
15885 case MVT::v4i32:
16013 // Example: from MVT::v2i32 to MVT::v4i32.
18689 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
18691 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19014 if (InputVector.getValueType() != MVT::v4i32)
19109 case MVT::v4i32:
19646 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
19671 if (VT == MVT::v4i32 || VT == MVT::v4f32)
19676 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
19677 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
19678 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
19685 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
19686 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
19707 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20294 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21514 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
21515 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
21526 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
21527 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
21701 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
21811 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
21814 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
21910 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21943 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22632 case MVT::v4i32:
