Lines Matching refs:v8f64
1332 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1345 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1358 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1363 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1419 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
22645 case MVT::v8f64:
