Lines Matching refs:v8i32
1139 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1178 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1181 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1200 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1209 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1236 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1241 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1246 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1250 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1259 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1264 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1269 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1277 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1280 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1282 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1307 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1378 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1382 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1389 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1699 return MVT::v8i32;
1807 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
4027 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4910 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4947 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4950 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
6425 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6468 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6514 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6524 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6625 SDValue ZeroVec = getZeroVector(MVT::v8i32
8584 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8585 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9512 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9547 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11081 // v8i16 -> v8i32
11093 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11227 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11228 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11244 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11245 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12766 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
12774 // Sign extend v8i16 to v8i32 and
15081 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15157 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15177 if (VT == MVT::v8i32) {
15220 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15388 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15455 case MVT::v8i32:
15466 case MVT::v8i32:
15479 case MVT::v8i32:
15546 VT == MVT::v4i64 || VT == MVT::v8i32))
15550 VT == MVT::v4i64 || VT == MVT::v8i32))
15552 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
15715 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
15716 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
15719 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
15857 case MVT::v8i32:
19101 case MVT::v8i32:
20296 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21814 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
21911 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21944 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22640 case MVT::v8i32:
