Lines Matching refs:v8i64
1331 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1346 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1394 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1402 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1411 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1420 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1423 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1426 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1431 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1440 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1441 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1442 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1448 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1480 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1488 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
9777 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9975 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11128 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11206 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12740 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15062 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15063 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15222 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15389 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15458 case MVT::v8i64:
15469 case MVT::v8i64:
15482 case MVT::v8i64:
15492 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15540 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
22648 case MVT::v8i64:
