Lines Matching refs:v16i16
192 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
193 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
220 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
223 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
226 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
231 { ISD::SDIV, MVT::v16i16, 16*20 },
235 { ISD::UDIV, MVT::v16i16, 16*20 },
242 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
245 // On AVX2, a packed v16i16 shift left by a constant build_vector
356 { ISD::MUL, MVT::v16i16, 4 },
374 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a
376 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) &&
430 if (ST->hasAVX2() && LT.second == MVT::v16i16)
442 {ISD::VECTOR_SHUFFLE, MVT::v16i16, 5},
569 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
570 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
596 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
597 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
618 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
707 { ISD::SETCC, MVT::v16i16, 4 },
714 { ISD::SETCC, MVT::v16i16, 1 },
