Lines Matching refs:v8i32
194 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
195 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
206 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
211 { ISD::SHL, MVT::v8i32, 1 },
212 { ISD::SRL, MVT::v8i32, 1 },
213 { ISD::SRA, MVT::v8i32, 1 },
232 { ISD::SDIV, MVT::v8i32, 8*20 },
236 { ISD::UDIV, MVT::v8i32, 8*20 },
357 { ISD::MUL, MVT::v8i32, 4 },
358 { ISD::SUB, MVT::v8i32, 4 },
359 { ISD::ADD, MVT::v8i32, 4 },
374 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a
376 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) &&
437 {ISD::VECTOR_SHUFFLE, MVT::v8i32, 1}, // vblendps
571 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
572 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
573 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
574 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
575 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
576 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
589 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
590 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
591 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
598 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
599 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
600 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
601 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
602 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
603 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
616 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
617 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
619 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
624 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
637 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
661 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
706 { ISD::SETCC, MVT::v8i32, 4 },
713 { ISD::SETCC, MVT::v8i32, 1 },
866 { ISD::ADD, MVT::v8i32, 5 },
885 { ISD::ADD, MVT::v8i32, 5 },
