Lines Matching defs:DAG
1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
177 // We have target-specific dag combine patterns for the following nodes:
206 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
209 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
210 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
211 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
212 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
213 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
214 case ISD::LOAD: return LowerLOAD(Op, DAG);
215 case ISD::STORE: return LowerSTORE(Op, DAG);
216 case ISD::VAARG: return LowerVAARG(Op, DAG);
217 case ISD::VASTART: return LowerVASTART(Op, DAG);
218 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
219 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
222 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
223 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
224 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
225 case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
226 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
227 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
228 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
229 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
230 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
231 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG);
241 SelectionDAG &DAG) const {
247 Results.push_back(ExpandADDSUB(N, DAG));
258 SelectionDAG &DAG) const {
263 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
268 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
270 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
286 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
295 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset);
296 GA = getGlobalAddressWrapper(GA, GV, DAG);
299 SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, MVT::i32);
300 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
305 Type *Ty = Type::getInt8PtrTy(*DAG.getContext());
307 Ty = Type::getInt32Ty(*DAG.getContext());
310 SDValue CP = DAG.getConstantPool(GAI, MVT::i32);
311 return DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), CP,
317 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
322 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
324 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
328 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
336 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
339 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
342 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
350 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
358 MachineFunction &MF = DAG.getMachineFunction();
360 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
364 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
367 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
368 DAG.getConstant(1, MVT::i32));
369 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
375 int64_t Offset, SelectionDAG &DAG) const
378 return DAG.getLoad(getPointerTy(), DL, Chain, Base, MachinePointerInfo(),
387 LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
389 HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
392 LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
393 DAG.getConstant(LowOffset, MVT::i32));
394 HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
395 DAG.getConstant(HighOffset, MVT::i32));
397 SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32);
398 SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32);
400 SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
403 SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
406 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
407 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
408 SDValue Result = DAG
409 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
412 return DAG.getMergeValues(Ops, DL);
415 static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
418 DAG.computeKnownBits(Value, KnownZero, KnownOne);
423 LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
433 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
445 if (DAG.isBaseWithConstantOffset(BasePtr) &&
446 isWordAligned(BasePtr->getOperand(0), DAG)) {
450 Offset, DAG);
454 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL,
457 Offset, DAG);
462 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
465 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
466 DAG.getConstant(2, MVT::i32));
467 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
472 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
473 DAG.getConstant(16, MVT::i32));
474 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
475 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
478 return DAG.getMergeValues(Ops, DL);
482 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
490 TargetLowering::CallLoweringInfo CLI(DAG);
493 DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
498 return DAG.getMergeValues(Ops, DL);
502 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
511 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
523 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
524 DAG.getConstant(16, MVT::i32));
525 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
529 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
530 DAG.getConstant(2, MVT::i32));
531 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
535 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
539 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
550 TargetLowering::CallLoweringInfo CLI(DAG);
552 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
553 DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
561 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
568 SDValue Zero = DAG.getConstant(0, MVT::i32);
569 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
570 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
574 return DAG.getMergeValues(Ops, dl);
578 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
585 SDValue Zero = DAG.getConstant(0, MVT::i32);
586 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
587 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
591 return DAG.getMergeValues(Ops, dl);
654 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
669 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
670 Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
671 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
672 Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
673 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
674 Other, DAG.getConstant(0, MVT::i32));
675 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
676 Other, DAG.getConstant(1, MVT::i32));
678 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
679 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
680 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
681 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
683 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
684 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
687 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
691 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
692 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
698 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
699 Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
700 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
701 Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
702 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
703 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
706 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
707 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
708 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
709 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
710 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
714 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
721 SDValue Result = TryExpandADDWithMul(N, DAG);
729 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
730 N->getOperand(0), DAG.getConstant(0, MVT::i32));
731 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
732 N->getOperand(0), DAG.getConstant(1, MVT::i32));
733 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
734 N->getOperand(1), DAG.getConstant(0, MVT::i32));
735 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
736 N->getOperand(1), DAG.getConstant(1, MVT::i32));
741 SDValue Zero = DAG.getConstant(0, MVT::i32);
742 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
746 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
750 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
754 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
765 SDValue VAList = DAG.getLoad(PtrVT, dl, InChain,
769 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
770 DAG.getIntPtrConstant(VT.getSizeInBits() / 8));
772 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
775 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
780 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
785 MachineFunction &MF = DAG.getMachineFunction();
787 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
788 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
793 SelectionDAG &DAG) const {
794 // This nodes represent llvm.frameaddress on the DAG.
802 MachineFunction &MF = DAG.getMachineFunction();
804 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op),
809 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
810 // This nodes represent llvm.returnaddress on the DAG.
818 MachineFunction &MF = DAG.getMachineFunction();
821 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
822 return DAG.getLoad(getPointerTy(), SDLoc(Op), DAG.getEntryNode(), FIN,
828 LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const {
833 return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32);
837 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
842 MachineFunction &MF = DAG.getMachineFunction();
850 SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
852 SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl,
854 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs);
855 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset);
863 DAG.getCopyToReg(Chain, dl, StackReg, Stack),
864 DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)
867 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
869 return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain,
870 DAG.getRegister(StackReg, MVT::i32),
871 DAG.getRegister(HandlerReg, MVT::i32));
876 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
881 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
905 OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
909 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
910 DAG.getConstant(4, MVT::i32));
911 OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
915 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
916 DAG.getConstant(8, MVT::i32));
917 OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
921 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
922 DAG.getConstant(12, MVT::i32));
923 OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
927 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
928 DAG.getConstant(16, MVT::i32));
929 OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
933 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
937 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
944 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
948 return DAG.getMergeValues(Results, DL);
954 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
956 return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
960 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const {
968 return DAG.getLoad(getPointerTy(), SDLoc(Op), N->getChain(),
977 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
983 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
991 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const {
999 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(),
1007 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
1013 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
1034 SelectionDAG &DAG = CLI.DAG;
1056 Outs, OutVals, Ins, dl, DAG, InVals);
1065 SDLoc dl, SelectionDAG &DAG,
1072 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
1090 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1091 SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
1092 SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
1100 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1116 SDLoc dl, SelectionDAG &DAG,
1121 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1122 getTargetMachine(), ArgLocs, *DAG.getContext());
1132 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1133 getTargetMachine(), RVLocs, *DAG.getContext());
1140 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
1156 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1159 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1162 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1175 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
1177 DAG.getConstant(Offset/4, MVT::i32)));
1184 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1192 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1201 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
1203 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
1209 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1217 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1223 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops);
1227 Chain = DAG.getCALLSEQ_END(Chain,
1228 DAG.getConstant(NumBytes, getPointerTy(), true),
1229 DAG.getConstant(0, getPointerTy(), true),
1235 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1253 SelectionDAG &DAG,
1263 Ins, dl, DAG, InVals);
1278 SelectionDAG &DAG,
1280 MachineFunction &MF = DAG.getMachineFunction();
1287 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1288 getTargetMachine(), ArgLocs, *DAG.getContext());
1331 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1351 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1352 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1380 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1384 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1387 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1401 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode);
1415 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1417 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
1418 DAG.getConstant(Size, MVT::i32),
1430 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1459 SDLoc dl, SelectionDAG &DAG) const {
1462 DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
1463 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1470 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1471 getTargetMachine(), RVLocs, *DAG.getContext());
1483 RetOps.push_back(DAG.getConstant(0, MVT::i32));
1503 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1504 MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN,
1512 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1520 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1525 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1534 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps);
1609 SelectionDAG &DAG = DCI.DAG;
1624 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1626 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1641 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1663 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1667 SDValue Carry = DAG.getConstant(0, VT);
1668 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1669 DAG.getConstant(1, VT));
1671 return DAG.getMergeValues(Ops, dl);
1680 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1682 SDValue Carry = DAG.getConstant(0, VT);
1683 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1685 return DAG.getMergeValues(Ops, dl);
1703 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1706 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1707 DAG.getConstant(0, VT), N2);
1709 return DAG.getMergeValues(Ops, dl);
1719 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1721 SDValue Borrow = DAG.getConstant(0, VT);
1722 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1724 return DAG.getMergeValues(Ops, dl);
1741 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1748 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1750 return DAG.getMergeValues(Ops, dl);
1754 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1757 return DAG.getMergeValues(Ops, dl);
1769 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1770 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1782 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1783 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1784 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1785 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1786 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1787 Mul0, DAG.getConstant(0, MVT::i32));
1788 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1789 Mul1, DAG.getConstant(0, MVT::i32));
1790 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1791 Addend0, DAG.getConstant(0, MVT::i32));
1792 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1793 Addend1, DAG.getConstant(0, MVT::i32));
1794 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1795 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1798 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1817 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1828 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1830 DAG.getConstant(StoreBits/8, MVT::i32),
1844 const SelectionDAG &DAG,
