Lines Matching full:align
18 %0 = load <4 x i8>* %v, align 8
22 store <4 x i32> %v1, <4 x i32>* undef, align 8
31 %0 = load <2 x i8>* %v, align 8
35 store <2 x i64> %v1, <2 x i64>* undef, align 8
44 %0 = load <2 x i16>* %v, align 8
48 store <2 x i64> %v1, <2 x i64>* undef, align 8
59 %0 = load <4 x i8>* %v, align 8
62 %1 = load <4 x i8>* %p, align 8
66 store <4 x i32> %v1, <4 x i32>* undef, align 8
75 %0 = load <2 x i8>* %v, align 8
78 %1 = load <2 x i8>* %p, align 8
82 store <2 x i64> %v1, <2 x i64>* undef, align 8
91 %0 = load <2 x i16>* %v, align 8
94 %1 = load <2 x i16>* %p, align 8
98 store <2 x i64> %v1, <2 x i64>* undef, align 8
109 %0 = load <4 x i8>* %v, align 8
112 %1 = load <4 x i16>* %p, align 8
116 store <4 x i32> %v1, <4 x i32>* undef, align 8
125 %0 = load <2 x i8>* %v, align 8
128 %1 = load <2 x i16>* %p, align 8
132 store <2 x i64> %v1, <2 x i64>* undef, align 8
141 %0 = load <2 x i16>* %v, align 8
144 %1 = load <2 x i32>* %p, align 8
148 store <2 x i64> %v1, <2 x i64>* undef, align 8
