Lines Matching refs:dcl
102 bool handleDeclaration(const sm4_dcl& dcl);
103 bool inspectDeclaration(const sm4_dcl& dcl);
842 Converter::inspectDeclaration(const sm4_dcl& dcl)
847 if (dcl.op.get() && dcl.op->is_index_simple(0))
848 idx = dcl.op->indices[0].disp;
850 switch (dcl.opcode) {
853 shadow[idx] = dcl.dcl_sampler.shadow;
857 enum sm4_target targ = (enum sm4_target)dcl.dcl_resource.target;
868 info.immd.bufSize = dcl.num * 4;
870 memcpy(info.immd.buf, dcl.data, info.immd.bufSize);
880 ipa_mode = (enum sm4_interpolation)dcl.dcl_input_ps.interpolation;
888 if (dcl.op->file == SM4_FILE_INPUT_DOMAIN_POINT) {
891 info.in[idx].mask = dcl.op->mask;
897 switch (dcl.sv) {
910 switch (dcl.op->file) {
933 nrRegVals += dcl.num;
940 info.prop.fp.earlyFragTests = dcl.dcl_global_flags.early_depth_stencil;
953 dcl.dcl_gs_output_primitive_topology.primitive_topology);
956 info.prop.gp.inputPrim = g3dPrim(dcl.dcl_gs_input_primitive.primitive);
959 info.prop.gp.maxVertices = dcl.num;
962 info.prop.gp.instanceCount = dcl.num;
970 dcl.dcl_input_control_point_count.control_points;
974 dcl.dcl_output_control_point_count.control_points;
977 switch (dcl.dcl_tess_domain.domain) {
994 switch (dcl.dcl_tess_partitioning.partitioning) {
1012 switch (dcl.dcl_tess_output_primitive.primitive) {
1082 bool Converter::handleDeclaration(const sm4_dcl& dcl)
1084 switch (dcl.opcode) {
1087 dcl.indexable_temp.num, dcl.indexable_temp.comps,
1089 arrayVol += dcl.indexable_temp.num * dcl.indexable_temp.comps * 4;
1102 phaseInstCnt[0][subPhaseCnt[0] - 1] = dcl.num;
1105 phaseInstCnt[1][subPhaseCnt[1] - 1] = dcl.num;
