Lines Matching defs:DAG
1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file is
258 // Custom DAG Lowering Operations
261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
275 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
277 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
294 SelectionDAG &DAG,
299 SDValue OpNode = DAG.getNode(VCCNode, DL, MVT::i64,
300 DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64,
302 DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64,
305 return DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i1, OpNode);
308 SDValue SITargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
317 CmpValue = DAG.getNode(
324 Result = DAG.getNode(
332 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
374 SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
385 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
389 // Custom DAG optimizations
394 SelectionDAG &DAG = DCI.DAG;
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
430 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
