Lines Matching defs:vs
44 struct brw_vs_unit_state *vs;
46 vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
47 sizeof(*vs), 32, &brw->vs.state_offset);
48 memset(vs, 0, sizeof(*vs));
51 vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
52 vs->thread0.kernel_start_pointer =
54 brw->vs.state_offset +
56 brw->vs.prog_offset +
57 (vs->thread0.grf_reg_count << 1)) >> 6;
59 vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
72 vs->thread1.single_program_flow = (intel->gen == 5);
74 vs->thread1.binding_table_entry_count = 0;
76 if (brw->vs.prog_data->total_scratch != 0) {
77 vs->thread2.scratch_space_base_pointer =
78 brw->vs.scratch_bo->offset >> 10; /* reloc */
79 vs->thread2.per_thread_scratch_space =
80 ffs(brw->vs.prog_data->total_scratch) - 11;
82 vs->thread2.scratch_space_base_pointer = 0;
83 vs->thread2.per_thread_scratch_space = 0;
86 vs->thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length;
87 vs->thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length;
88 vs->thread3.dispatch_grf_start_reg = 1;
89 vs->thread3.urb_entry_read_offset = 0;
92 if (ctx->Transform.ClipPlanesEnabled && !brw->vs.prog_data->uses_new_param_layout) {
96 vs->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
99 vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
117 vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
135 vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
138 vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
140 vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
147 vs->vs5.sampler_count = 0;
150 vs->thread4.stats_enable = 1;
154 vs->vs6.vs_enable = 1;
157 if (brw->vs.prog_data->total_scratch != 0) {
159 brw->vs.state_offset +
161 brw->vs.scratch_bo,
162 vs->thread2.per_thread_scratch_space,
